• Title/Summary/Keyword: Operation timing

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Performance and Emission Comparisons of a SI Engine Fueled by Syngas with Varying Hydrogen Content (합성가스 연료의 수소 함량 변화가 SI 엔진의 연소특성에 주는 영향)

  • Park, Seung-Hyun;Lee, Sun-Youp;Park, Cheol-Woong;Lee, Jang-Hee
    • Journal of the Korean Institute of Gas
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    • v.15 no.2
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    • pp.63-68
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    • 2011
  • As an effective utilization of biomass, organic wastes and coal, attention has been made to use syngas to a reciprocating engine to generate power. However, significant component variation of syngas depending upon origin and gasification conditions, and its lower heating value than that of LPG and CNG can create difficulties in stable engine operation. Thus it is necessary to address these issues in order to successfully develop power generation engines. As a primary step to resolve these problems, effects of H2 content variation in syngas on engine performance and emission characteristics were discussed in this study. The results show that as H2 % in syngas increases, more stable combustion was achieved with retarded MBT spark timing and engine efficiency becomes maximum with syngas of 10% H2. In addition, NOx emission increased while THC emission decreased as H2 % rises in the syngas.

Hardware Implementation of Chaotic System for Security of JPEG2000 (JPEG2000의 보안을 위한 카오스 시스템의 하드웨어 구현)

  • Seo Young-Ho
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.12C
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    • pp.1193-1200
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    • 2005
  • In this paper, we proposed an image hiding method which decreases the amount of calculation encrypting partial data rather than the whole image data using a discrete wavelet transform and a linear scalar quantization which have been adopted as the main technique in JPEG2000 standard and then implemented the proposed algorithm to hardware. A chaotic system was used instead of encryption algorithms to reduce further amount of calculation. It uses a method of random changing method using the chaotic system of the data in a selected subband. For ciphering the quantization index it uses a novel image encryption algorithm of cyclical shifting to the right or left direction and encrypts two quantization assignment method (Top-down coding and Reflection coding), made change of data less. The experiments have been performed with the proposed methods implemented in software for about 500 images. The hardware encryption system was synthesized to find the gate-level circuit with the Samsung $0.35{\mu}m$ Phantom-cell library and timing simulation was performed, which resulted in the stable operation in the frequency above 100MHz.

TDoA-Based Practical Localization Using Precision Time-Synchronization (정밀 시각동기를 이용한 TDoA 기반의 위치 탐지)

  • Kim, Jae-Wan;Eom, Doo-Seop
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38C no.2
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    • pp.141-154
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    • 2013
  • The technology of precise time-synchronization between signal receive devices for separation distance operation can be a key point for the technology with TDoA-based system. We propose a new method for the higher accuracy of system's time-synchronization in this paper, which uses OCXO and DPLL with high accuracy to achieve phase synchronization at 1 pps (pulse per second) of signal. And the method receive time value from a GPS satellite. Essentially, the performance of GPS with high accuracy refers to long-term frequency stability for its reliability. As per the characteristic, as the GPS timing signals are synchronized continuously, the accuracy of time-synchronization gets improved proportionally. Therefore, if the time synchronization is accomplished, the accuracy of the synchronization can be up to 0.001 ppb (part per billion). Through the improved accuracy of the time-synchronization, the measurement error of TDOA-based location detection technology is evaluated. Consequently, we verify that TDoA-based location measurement error can be greatly improved via using the improved method for time-synchronization error.

A Study on the Problem-Solving Method and Thermal Efficiency Properties at the Time of High Expansion Realization in a 4-Cycle Diesel Engine (4사이클 디젤기관에서 고팽창 실현 시 문제점 해결방안과 열효율 특성에 대한 연구)

  • Jang, Tae-Ik
    • Journal of Advanced Marine Engineering and Technology
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    • v.33 no.6
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    • pp.835-842
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    • 2009
  • The present thesis carried out a research on a compression pressure's reduction phenomenon and its countermeasure according to the thermal efficiency improvement method by a Miller method in 4-cycle low speed diesel engine. In case of retardation of intake valve closing time in a engine, the theoretical heat efficiency shows a remarkably reducing trend when a compression ratio is not compensated. Accordingly, the thermal efficiency showed an increasing trend in case of compensating the compression ratio. Especially, it could be understood that the theoretical heat efficiency at near ABDC $100^{\circ}$ of intake valve closing time in case of compensation of the compression ratio was improved by around 25.1%, and the mean effective pressure was also increased by around 18.6%. Also, as the retardation of intake valve closing time increases, air quantity becomes insufficient due to a backflow phenomenon of intake air and thus thermal efficiency was decreased in a high load operation domain. The solving method of this problem is possible by supercharge. Therefore, in order to improve thermal efficiency by retardation of ntake valve closing time, the thermal efficiency improvement according to low compression is possible when there are a compensation device of a compression ratio and a supercharge device. This is a problem-solving method of low compression and high expansion cycle.

POSTOPERATIVE RECURRENCES OF ODONTOGENIC KERATOCYST : THE BEHAVIOR AND PROPOSAL OF CRITICAL FOLLOW-UP PERIOD (치성 각화 낭종의 술후 재발양상과 추적관찰 기간의 제안)

  • Park, Se-Hyun;Kim, Nam-Kyun;Kim, Ki-Ho;Kang, Sang-Hoon;Park, Hyung-Sik;Kim, Hyung-Jun;Cha, In-Ho;Nam, Woong
    • Journal of the Korean Association of Oral and Maxillofacial Surgeons
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    • v.34 no.4
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    • pp.456-459
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    • 2008
  • Post-operative recurrence of cystic lesion is a great concern for clinician, patients, and their family, especially in case of odontogenic keratocyst, which has aggressive behavior and high recurrence rate. The purpose of this study was to evaluation clinical characters of OKC, focusing of the recurrence rate and proposed critical follow-up period. 58 cases (aged 9 to 66, 33 males and 25 females) of OKC were reviewed for sex of patients, location, size, operative procedure type, radiographic findings, histopathologic findings, post-operative recurrence time, from 2000 to 2005 at Yonsei Medical Center, were selected. The computerized statistical analysis was carried out with SAS system. 18 of 58 cases (31.03%) were recurred and this study revealed no statistically significant difference in recurrence rate for sex, location, size, radiographic findings, histopatologic findings, operative procedure type, recurrence timing. 3 out of 18 cases (16.7%) showed one or more recurrence. This was statistically significant difference (P=.0264). In this study, 15 of 18 cases (83.3%) were observed recurrence during 4 years after removal of the OKCs, we suggest critical follow-up period during 4 years after operation.

A Prognosis Evaluation after Iliac Bone Graft in Cleft Alveolus Patients (치조열 환자의 장골이식술 후 예후 평가)

  • Hong Jin-Ho;Soh Byung-Soo;Baik Jin-Ah;Shin Hyo-Keun
    • Korean Journal of Cleft Lip And Palate
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    • v.4 no.2
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    • pp.69-78
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    • 2001
  • Alveolar cleft exists in 75% of cleft patients, In alveolar cleft patients, alar base is widening, palatal fistular formation, maxillary growth disturbance & tooth loss of adjacent area is raised, Alveolar bone grafting, especially iliac bone grafting, is a general treatment method. As operation timing, bone grafting is classified with primary, early secondary, secondary, & late secondary, Here we report cleft width, marginal bone height, bone resorption rate, grafted shape & bone densities after secondary iliac bone grafting was done in the Dept. of oral and maxillofacial surgery of chonbuk national university hospital. We compared cleft width to bone resorption rate and grafted shape. Also, alveolar bone densities of grafted and contralateral site was compared with Emago 3 package? (Oral Diagonostic System, The Netherlands), The data obtained were analyzed using Spearman's rho coefficients and sign test with SPSS for window, The results were obtained as follows. 1. As alveolar cleft width is increase, bone resorption rate is, too. This relation showed significant difference(P<.01). 2, In proximal & distal area, alvolar cleft width and bone graft contour after bone grafting had a reverse proportional difference. It was not significant difference(P>.05). 3. After 3 month, in bone density results by using Emago 3 package? with periapical standard view, occlusal view & panoramic view, differences between grafted bone and alveolar bone of contralateral site didn't show a significant difference(P>.05). Thus, differences of bone densities in the alveolar bones didn't exist.

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Scalable Dual-Field Montgomery Multiplier Using Multi-Precision Carry Save Adder (다정도 CSA를 이용한 Dual-Field상의 확장성 있는 Montgomery 곱셈기)

  • Kim, Tae-Ho;Hong, Chun-Pyo;Kim, Chang-Hoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.1C
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    • pp.131-139
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    • 2008
  • This paper presents a scalable dual-field Montgomery multiplier based on a new multi-precision carry save adder(MP-CSA), which operates in both types of finite fields GF(p) and GF($2^m$). The new MP-CSA consists of two carry save adders(CSA). Each CSA is composed of n = [w/b] carry propagation adders(CPA) for a modular multiplication with w-bit words, where b is the number of dual field adders(DFA) in a CPA. The proposed Montgomery multiplier has roughly the same timing complexity compared with the previous result, however, it has the advantage of reduced chip area requirements. In addition, the proposed circuit produces the exact modular multiplication result at the end of operation unlike the previous architecture. Furthermore, the proposed Montgomery multiplier has a high scalability in terms of w and m. Therefore, it can be used to multiplier over GF(p) and GF($2^m$) for cryptographic applications.

Low Power High Frequency Design for Data Transfer for RISC and CISC Architecture (RISC와 CISC 구조를 위한 저전력 고속 데이어 전송)

  • Agarwal Ankur;Pandya A. S.;Lho Young-Uhg
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.2
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    • pp.321-327
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    • 2006
  • This paper presents low power and high frequency design of instructions using ad-hoc techniques at transistor level for full custom and semi-custom ASIC(Application Specific Integrated Circuit) designs. The proposed design has been verified at high level using Verilog-HDL and simulated using ModelSim for the logical correctness. It is then observed at the layout level using LASI using $0.25{\mu}m$ technology and analyzed for timing characteristic under Win-spice simulation environment. The result shows the significant reduction up to $35\%$ in the power consumption by any general purpose processor like RISC or CISC. A significant reduction in the propagation delay is also observed. increasing the frequency for the fetch and execute cycle for the CPU, thus increasing the overall frequency of operation.

Three-Phase PWM Inverter and Rectifier with Two-Switch Auxiliary Resonant DC Link Snubber-Assisted

  • Nagai Shinichiro;Sato Shinji;Matsumoto Takayuki
    • Journal of Power Electronics
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    • v.5 no.3
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    • pp.233-239
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    • 2005
  • In this paper, a new conceptual circuit configuration of a 3-phase voltage source, soft switching AC-DC-AC converter using an IGBT module, which has one ARCPL circuit and one ARDCL circuit, is presented. In actuality, the ARCPL circuit is applied in the 3-phase voltage source rectifier side, and the ARDCL circuit is in the inverter side. And more, each power semiconductor device has a novel clamp snubber circuit, which can save the power semiconductor device from voltage and current across each power device. The proposed soft switching circuits have only two active power semiconductor devices. These ARCPL and ARDCL circuits consist of fewer parts than the conventional soft switching circuit. Furthermore, the proposed 3-phase voltage source soft switching AC-DC-AC power conversion system needs no additional sensor for complete soft switching as compared with the conventional 3-phase voltage source AC-DC-AC power conversion system. In addition to this, these soft switching circuits operate only once in one sampling term. Therefore, the power conversion efficiency of the proposed AC-DC-AC converter system will get higher than a conventional soft switching converter system because of the reduced ARCPL and ARDCL circuit losses. The operation timing and terms for ARDCL and ARCPL circuits are calculated and controlled by the smoothing DC capacitor voltage and the output AC current. Using this control, the loss of the soft switching circuits are reduced owing to reduced resonant inductor current in ARCPL and ARDCL circuits as compared with the conventional controlled soft switching power conversion system. The operating performances of proposed soft switching AC-DC-AC converter treated here are evaluated on the basis of experimental results in a 50kVA setup in this paper. As a result of experiment on the 50kVA system, it was confirmed that the proposed circuit could reduce conduction noise below 10 MHz and improve the conversion efficiency from 88. 5% to 90.5%, when compared with the hard switching circuit.

A Study of Delay Test for Sequential circuit based on Boundary Scan Architecure (순서회로를 위한 경계면 스캔 구조에서의 지연시험 연구)

  • Lee, Chang-Hee;Kim, Jeong-Hwan;Yun, Tae-Jin;Nam, In-Gil;Ahn, Gwang-Seon
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.3
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    • pp.862-872
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    • 1998
  • In this paper, we developed a delay test architecture and test procedure for clocked sequential circuit. In addition, we analyze the problems of conventional and previous method on delay test for clocked sequential circuit in IEEE 1149.1. This paper discusses several problems of Delay test on IEEE 1149.1 for clocked sequential circuit. Previous method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a method called ARCH-S, is based on a clock counting technique to generate continuous clocks for clocked input of CUT. A 4-bit counter is selected for the circuit under test. The simulation results ascertain the aecurate operation and effectiveness of the proposed architecture.

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