• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.3
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• pp.397-404
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• 2011

In this research, wish to suggest method to embody system that can accommodate defect of PLC and find actual propriety. Defect permission control system minimizes production damage because enables repair and checking without discontinuance and improve believability about whole system. Propose duplexing of system to embody this fault tolerant system. Therefore, composed control system that can permit defect or breakdown duplexings of various module proposing this system, and confirms to simulation and actuality kiln of defect permission control system through an application experiment, and compares for mean time between defect by estimate and defect special quality and system configuration of failure(failure) to improve believability of PLC control system together. In proposed system expression method and system mode and relation with operation mode, error discovery mode and switching tube of duplexing mode, and PLC's central processing unit of node study algorithm about master-standby conversion driving and continuous operation of 2 channels method that have 2 that is not one and deduced continuous operation method and result about defect permission in this algorithm and applies this result to actuality kiln control system and confirms continuous operation about PLC defect permission.

• Journal of Advanced Navigation Technology
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• v.17 no.5
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• pp.497-505
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• 2013

In TETRA(TErrestrial Trunked RAdio) standard, TMO(Trunked Mode Operation) communicates with the UE through the base station and it has a higher priority than DMO(Direct Mode Operation) which communicates with UE directly for channel allocation. As a result, the UE needs an algorithm which restricts the frequency allocation by TMO so that DMO can have a successful communication within the network. However, the TETRA DMO standard does not consider this issue. In this paper, we propose an active DMO channel selection algorithm which allocates a channel based on some additional information such as channel usage state of TMO and channel utilization of DMO. The experimental results show that the proposed algorithm outperforms existing DMO channel allocation scheme in terms of the transmission efficiency.

• Journal of IKEEE
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• v.22 no.2
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• pp.233-241
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• 2018

This paper describes a lightweight implementation of a cryptographic processor supporting GCM (Galois/Counter Mode) authenticated encryption (AE) that is based on the two block cipher algorithms of ARIA and AES. It also provides five modes of operation (ECB, CBC, OFB, CFB, CTR) for confidentiality as well as the key lengths of 128-bit and 256-bit. The ARIA and AES are integrated into a single hardware structure, which is based on their algorithm characteristics, and a $128{\times}12-b$ partially parallel GF (Galois field) multiplier is adopted to efficiently perform concurrent processing of CTR encryption and GHASH operation to achieve overall performance optimization. The hardware operation of the ARIA/AES-GCM AE processor was verified by FPGA implementation, and it occupied 60,800 gate equivalents (GEs) with a 180 nm CMOS cell library. The estimated throughput with the maximum clock frequency of 95 MHz are 1,105 Mbps and 810 Mbps in AES mode, 935 Mbps and 715 Mbps in ARIA mode, and 138~184 Mbps in GCM AE mode according to the key length.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.34 no.5
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• pp.833-840
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• 2024

Existing side-channel analysis studies have mostly been analyzed only on block ciphers without considering the operation mode. However, establishing a methodology of side-channel analysis on operation mode is necessary because information for performing analysis varies depending on that. This paper proposes a methodology of correlation power analysis (CPA) on an operation mode CBC in a software target. The first round SubBytes layer output is generally used as a sensitive hypothetical intermediate value of an encryption algorithm AES (advanced encryption standard); however, the adversary should acquire the plaintext and ciphertext to calculate the input of AES in CBC mode. We propose an intermediate value calculated only by ciphertext. Besides, the initial vector (IV) could be treated as closed information in practice, although it is theoretically not secret. The adversary cannot decrypt the first block of plaintext without IV even if he analyzes the secret key. We propose a deep learning-based IV analysis method in a non-profiled environment.

• Journal of Mechanical Science and Technology
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• v.15 no.3
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• pp.339-350
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• 2001

To overcome problems in tracking error related to the unmodeled dynamics in the high speed operation of industrial robots, many researchers have used sliding mode control, which is robust against parameter variations and payload changes. However, these algorithms cannot reduce the inherent chattering which is caused by excessive switching inputs around the sliding surface. This study proposes a fuzzy-sliding mode control algorithm to reduce the chattering of the sliding mode control by fuzzy rules within a pre-determined dead zone. Trajectory tracking simulations and experiments show that chattering can be reduced prominently by the fuzzy-sliding mode control algorithm compared to a sliding mode control with two dead zones, and the proposed control algorithm is robust to changes in payload. The proposed control algorithm is implemented to the SCARA (selected compliance articulated robot assembly) robot using a DSP (digital signal processor) for high speed calculations.

• Transactions of the Korean Society of Automotive Engineers
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• v.2 no.6
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• pp.9-17
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• 1994

In this study, a shifting algorithm of CVT was suggested for the two(2) driving modes : (1) power mode and (2) economy mode. Shifting algorithm must be obtained to make the engine run on the optimum operating line for the desired performance of the vehicle. Optimum operating lines of the engine were obtained by connecting the shortest way of the iso-power lines for the power mode and by connecting the shortest way of the BSFC curves for the economy mode. Also dynamic model of CVT vehicle was derived considering the throttle and the brake operation. By using the shifting algorithm and the CVT vehicle model, numerical simulations were performed to estimate the performance of CVT. Simulation results showed that comparing the performance of the conventional 4-speed automatic transmission, acceleration performance of the CVT vehicle was almost same with the AT vehicle for the power mode and the fuel economy of CVT was 14% superior than that of AT for the economy mode.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1582-1590
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• 2019

A new method for reducing the common-mode current generated by the voltage variations in a two-inverter air conditioner system by applying a synchronized pulse-width modulation (PWM) strategy is proposed. The PWM signals of the master-mode inverter are generated based on the reference voltage, while those of the slave-mode inverter are output in the opposite direction when the master-mode inverter changes its switching state. However, the slave-mode control results in a mismatch between the reference voltage and the actual output voltage that is modified by synchronized control operation. The proposed method is capable of reducing and controlling this voltage error by performing signal selection in the vector space of the slave-mode inverter, which mitigates the distortion of the phase current. The efficacy of this method in reducing conducted emissions has been validated both theoretically and experimentally.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.169-172
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• 2000

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

• Proceedings of the Korea Multimedia Society Conference
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• 2000.04a
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• pp.117-120
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• 2000

This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.147-148
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• 2011

In this paper, implementation of digital control for critical conduction mode power factor correction (PFC) rectifier is presented. Critical conduction mode is widely used in medium and low power conversion application due to its minimized MOSFET turn-on loss and diode reverse-recovery problem. However, it needs additional zero current detection circuit and maximum frequency limit to properly turn the MOSFET on and avoid the excessive switching loss in light load operation. This paper explains the digital IC implementation and verifies its operation with 200-W prototype PFC rectifier.