• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8B
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• pp.509-520
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• 2007

In this paper, we propose a real-time sensor node platform that guarantees the real-time scheduling of periodic and aperiodic tasks through a multitask-based software decomposition technique. Since existing sensor networking operation systems available in literature are not capable of supporting the real-time scheduling of periodic and aperiodic tasks, the preemption of aperiodic task with high priority can block periodic tasks, and so periodic tasks are likely to miss their deadlines. This paper presents a comprehensive evaluation of how to structure periodic or aperiodic task decomposition in real-time sensor-networking platforms as regard to guaranteeing the deadlines of all the periodic tasks and aiming to providing aperiodic tasks with average good response time. A case study based on real system experiments is conducted to illustrate the application and efficiency of the multitask-based dynamic component execution environment in the sensor node equipped with a low-power 8-bit microcontroller, an IEEE802.15.4 compliant 2.4GHz RF transceiver, and several sensors. It shows that our periodic and aperiodic task decomposition technique yields efficient performance in terms of three significant, objective goals: deadline miss ratio of periodic tasks, average response time of aperiodic tasks, and processor utilization of periodic and aperiodic tasks.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.138-142
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• 2004

In this paper, we present a new method for monitoring of ECU's sensor signals of vehicle. In order to measure the ECU's sensor signals, the interfaced circuit is designed to communicate ECU and the Embedded Linux is used to monitor communication result through Web the Embedded Linux system and this system is said "ECU Interface Part". In ECU Interface Part the interface circuit is designed to match voltage level between ECU and SA-1110 micro controller and interface circuit to communicate ECU according to the ISO, SAE communication protocol standard. Because Embedded Linux does not allow to access hardware directly in application level, anyone who wants to modify any low level hardware must develop device driver. To monitor ECU's sensor signals the most important thing is to match serial level between ECU and ECU Interface Part. It means to communicate correctly between two hardware we need to match voltage and signal level, and need to match baudrate. The voltage of SA-1110 is 0 ${\sim}$ +3.3V and ECU is 0 ${\sim}$ +12V and, ECU's communication Line K does multiple operation so, the interface circuit is used to match voltage and signal level. In Addition to ECU's baudrate is 10400bps, it's not standard baudrate in computer environment. So, we need to develop a device driver to control the interface circuit, and change baudrate. To monitor ECU's sensor signals through web there's a network socket program is working in Embedded Linux. It works as server program and manages user's connections and commands. Anyone who wants to monitor ECU's sensor signals he just only connect to Embedded Linux system with web browser then, Embedded Linux webserver will return the ActiveX webbased measurement software. It works in web browser and inits ECU, as a result it returns sensor signals through web. All the programs are developed with GCC(GNU C Compiler) and, webbased measurement software is developed with Borland C++ Builder.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.15-23
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• 2009

Microprocessors, which need correct arithmetic operations, have been the subject of in-depth research in relation to soft errors. Of the existing microprocessor devices, the memory cell is the most vulnerable to soft errors. Moreover, when soft errors emerge in a memory cell, the processes and operations are greatly affected because the memory cell contains important information and instructions about the entire process or operation. Users do not realize that if soft errors go undetected, arithmetic operations and processes will have unexpected outcomes. In the field of architectural design, the tool that is commonly used to detect and correct soft errors is the error check and correction code. The Itanium, IBM PowerPC G5 microprocessors contain Hamming and Rasio codes in their level-2 cache. This research, however, focuses on huge server devices and does not consider power consumption. As the operating and threshold voltage is currently shrinking with the emergence of high-density and low-power embedded microprocessors, there is an urgent need to develop ECC (error check correction) circuits. In this study, the in-output data of the level-2 cache were analyzed using SimpleScalar-ARM, and a 32-bit H-matrix for the level-2 cache of an embedded microprocessor is proposed. From the point of view of power consumption, the proposed H-matrix can be implemented using a schematic editor of Cadence. Therefore, it is comparable to the modified Hamming code, which uses H-spice. The MiBench program and TSMC 0.18 um were used in this study for verification purposes.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.11
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• pp.63-77
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• 1994

This paper describes the real-time system which, through analyzing a sequence of images, can extract motional information on a moving object and can contol servo equipment to always locate the moving object at the center of an image frame. An image is a vast amount of two-dimensional signal, so it takes a lot of time to analyze the whole quantity of a given image. Especially, the time needed to load pixels from a memory to processor increase exponentially as the size of an image increases. To solve such a problem and track a moving object in real-time, this paper addresses how to selectively search the spatial and time domain. Based on the selective search of spatial and time domain, this paper suggests various types of techniques which are essential in implementing a real-time tracking system. That is, this paper describes how to detect an entrance of a moving object in the field of view of a camera and the direction of the entrance, how to determine the time interval of adjacent images, how to determine nonstationary areas formed by a moving object and calculated velocity and position information of a moving object based on the determined areas, how to control servo equipment to locate the moving object at the center of an image frame, and how to properly adjust time interval(${\Delta}$t) to track an object taking variable speed.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.1
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• pp.26-34
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• 1999

According to increase of nonlinear power electronics equipment, active power filters have been researched and developed for many years to compensate harmonic disturbances and reactive power. However the commercial of active power filter is being proceeded slowly, because the cost of active power filter compared to the passive filter for harmonic and reactive power compensation is expensive. Especially, the use of DSP (Digital Signal Processing) chip, which is frequently used to control 3-phase active power filter, is a factor of increasing the cost of active power filters. On the other hand, the use of only analog controller makes the controller's circuits much more complicate and depreciates the flexibilities of controller. In this paper, a controller with low cost for 5[kVA] 3-phase active power filter system is designed. To reduce the expense of active filter system, the presented controller is composed of digital control part using Intel 80C196KC $\mu$P and analog control part using hysteresis controller for current control. Characteristic analysis of designed controller for active filter system is performed by computer simulation and compensating characteristics of the designed controller are verified by experiment.tegy can apply to the vector control, leading to better output torque capability in the ac motor drive system. This strategy is that in the overmodulation range, the d-axis output current is given a priority to regulate the flux well, instead the q-axis output curent is sacrificed. Therefore, the vector control even in the overmodulation PWM operation can be achieved well. For this purpose, the d-axis output voltage of a current controller to control the flux is conserved. the q-axis output voltage to control the torque is controlled to place the reference voltage vector on the hexagon boundary in case of the overmodulation. The validity of the proposed overall scheme is confirmed by simulation and experiments for a 22[kW] induction motor drive system.

• The KIPS Transactions:PartD
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• v.8D no.4
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• pp.347-360
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• 2001

The most expensive spatial operation in spatial databases is a spatial join which computes a combined table of which tuple consists of two tuples of the two tables satisfying a spatial predicate. Although the execution time of sequential processing of a spatial join has been so far considerably improved, the response time is not tolerable because of not meeting the requirements of interactive users. It is usually appropriate to use parallel processing to improve the performance of spatial join processing. However, as the number of processors increases, the efficiency of each processor decreases rapidly because of the disk bottleneck and the overhead of message passing. This paper proposes the method of task allocation to soften the disk bottleneck caused by accessing the shared disk at the same time, and to minimize message passing among processors. In order to evaluate the performance of the proposed method in terms of the number of disk accesses and message passing, we conduct experiments on the two kinds of parallel spatial join algorithms. The experimental tests on the MIMD parallel machine with shared disks show that the proposed semi-dynamic task allocation method outperforms the static and dynamic task allocation methods.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.8
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• pp.2968-2974
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• 2010

Nowadays, the PV systems have been focused on the grid connection between the power source and the grid. The PV inverter can be considered as the core of the whole system because of an important role in the grid-interfacing operation. An important issue in the inverter control is the load current regulation. In the literature, Proportional Integral (PI) controller, which is normally used in the current-controlled Voltage Source Inverter (VSI), cannot be a satisfactory controller for an AC system because of the steady-sate error and the poor disturbance rejection, especially in high-frequency range. Compared with conventional PI controller, Proportional Resonant (PR) controller can introduce an infinite gain at the fundamental frequency of the AC source; hence it can achieve the zero steady-state error without requiring the complex transformation and the de-coupling technique. Theoretical analyses of both PI and PR controller are presented and verified by simulation and experiment. Both controller are implemented in a 32-bit fixed-point TMS320F2812 DSP processor and evaluated on a 3kW experimental prototype PV Power Conditioning System (PCS). Simulation and experimental results are shown to verify the controller performances.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8A
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• pp.820-829
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• 2006

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Due to the request for high performance of current mobile systems, embedded SoC design needs a multi-processor to manage problems of high complexity and the data processing such as multimedia, DMB and image processing in real time. Interface module for communication between system buses and processors are required, since many IPs employ different protocols. High performance processors require interface module to minimize the latency of data transmission during read-write operation and to enhance the performance of a top level system. This paper proposes an automatic interface generation system based on FSM generated from the common protocol description sequence of a bus and an IP. The proposed interface does not use a buffer which stores data temporally causing the data transmission latency. Experimental results show that the area of the interface circuits generated by the proposed system is reduced by 48.5% on the average, when comparing to buffer-based interface circuits. Data transmission latency is reduced by 59.1% for single data transfer and by 13.3% for burst mode data transfer. By using the proposed system, it becomes possible to generate a high performance interface circuit automatically.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.101-109
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• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

• Spatial Information Research
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• v.12 no.1
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• pp.13-27
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• 2004

The current industrial development and the increase of population in Daecheong Reservoir basin have produced a rapid increase of wastewater discharge. This has resulted in problem of water quality control and management. Although many efforts have been carried out, reservoir water quality has not significantly improved. In this sense, the development of water quality management system is required to improve reservoir water quality. The goal of this study is to design a GIS-based water quality management system for the scientific water quality control and management in the Daecheong Reservoir. For general water quality analysis, WASP5 model was applied to the Daecheong Reservoir. A sensitivity analysis was made to determine significant parameters and an optimization was made to estimate optimal values. The calibration and verification were performed by using observed water quality data for Daecheong Reservoir. A water quality management system for Daecheong Reservoir was made by connecting the WASP5 model to ArcView. It allows a Windows-based Graphic User Interface(GUI) to implement all operation with regard to water quality analysis. The proposed water quality management system has capability for the on-line data process including water quality simulation, and has a post processor far the reasonable visualization for various output. The modeling system in this study will be an efficient NGIS(National Geographic Information System) far planning of reservoir water quality management.