• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.2
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• pp.202-208
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• 2001

A Switched Reluctance Motor(SRM) has double salient poles structure and the phase windings are wound in stator. SRM hase more simple structure that of other motor, thus manufacture cost is low, mechanically strong, reliable to a poor environment such as high temperature, and maintenance cost is low because of brushless. SRM needs position detector to get rotator position information for phase excitation and tachometer or encoder for constant speed operation. But, this paper doesn\`s use an encoder of high cost for velocity measurement of rotator. Instead of it, the algorithm for position detection and velocity estimation from simple slotted disk has been proposed and developed. To implement variable speed digital control system with velocity estimation algorithm, the TMS320F240-20MIPS fixed point arithmetic processor of TI corporation is used. The experimental results of the developing system are enable to control speed with wide range, not only single pulse, hard chopping mode and soft chopping, ut also variable speed control, and advance angle control.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1964-1980
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• 2016

This paper presents a new simplified harmonics extraction algorithm based on the synchronous reference frame (SRF) for an indirect current controlled (ICC) three-level neutral point diode clamped (NPC) inverter-based shunt active power filter (SAPF). The shunt APF is widely accepted as one of the most effective current harmonics mitigation tools due to its superior adaptability in dynamic state conditions. In its controller, the SRF algorithm which is derived based on the direct-quadrature (DQ) theory has played a significant role as a harmonics extraction algorithm due to its simple implementation features. However, it suffers from significant delays due to its dependency on a numerical filter and unnecessary computation workloads. Moreover, the algorithm is mostly implemented for the direct current controlled (DCC) based SAPF which operates based on a non-sinusoidal reference current. This degrades the mitigation performances since the DCC based operation does not possess exact information on the actual source current which suffers from switching ripples problems. Therefore, three major improvements are introduced which include the development of a mathematical based fundamental component identifier to replace the numerical filter, the removal of redundant features, and the generation of a sinusoidal reference current. The proposed algorithm is developed and evaluated in MATLAB / Simulink. A laboratory prototype utilizing a TMS320F28335 digital signal processor (DSP) is also implemented to validate effectiveness of the proposed algorithm. Both simulation and experimental results are presented. They show significant improvements in terms of total harmonic distortion (THD) and dynamic response when compared to a conventional SRF algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.103-111
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• 2002

In RNC of IMT-2000, main control processors such as ASP, ACP and OMP are responsible for call control function, and the high reliability and real-time property should be provided for it. So, the study of real-time fault-tolerant for it is needed. In this paper, we proposes an Task based duplication method, in which Tasks in active side operated on message unit and send the updated data to standby side after operation, log in the message to standby side for recovery during take-over. This scheme decreases the dual down and the complexity of synchronization procedure, and performs the synchronization more exactly because Tasks control the synchronization of system. This paper also proposes the fault detection and the fault handing method for effective implementation of Task based duplication. This scheme focus on increasing the fault detection rate and intercepting originally that fault data is send to standby side.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.92-99
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• 2005

In this paper, we present a high-level design methodology applied on a network system-on-a-chip(SOC) using SystemC. The main target of our approach is to get optimum performance parameters for high network address translation(NAT) throughput. The Fast Ethernet media access controller(MAC) and its direct memory access(DMA) controller are modeled with SystemC in transaction level. They are calibrated through the cycle-based measurement of the operation of the real Verilog register transfer language(RTL). The NAT throughput of the model is within $\pm$10% error compared to the output of the real evaluation board. Simulation speed of the model is more than 100 times laster than the RTL. The validated models are used for intensive architecture exploration to find the performance bottleneck in the NAT router.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.6
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• pp.273-283
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• 2008

Many embedded real-time systems have adopted processors supported with dynamic voltage scaling(DVS) recently. Power is one of the important metrics for optimization in the design and operation of embedded real-time systems. We can save considerable energy by using slowdown of processor supported with DVS. In this paper, we propose heuristic algorithms to calculate task slowdown factors for an efficient energy consumption in embedded real-time systems with task synchronization. The previous algorithm has a following constraint : given the tasks are ordered in a nondecreasing order of their relative deadline, the task slowdown factors computed are in a nonincreasing order. In this paper, we relax the constraint and propose heuristic algorithms which have the same time complexity that previous algorithm has and can save more energy. Experimental results show that the proposed algorithms are energy efficient.

• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.2
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• pp.15-24
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• 2016

GPS(Global Positioning System) location tracking is a method for taking the precise coordinates after the coordinates are obtained by a GPS receiver, and displaying them on the map. In this paper with WAVE(Wireless Access for Vehicular Environment) simulation, we show that various services such as vehicle tracking service, real-time road conditions service and logistics can go tracking service, control and operation services according to the vehicle position and the traveling direction by using the GPS position data. A vehicle tracking system using GPS is automatically able to manage multiple RCP when exchanging data between RMA and the RCP, and it provides rapid requests and responses. To verify that multiple sessions between RMA and RM, as well as multiple sessions between RMA and RCP are able to be implemented, we take RMA as a RCP application on an OBU, until the RMA is receiving data response from corresponding RM. As a result of this experiment, we show that the response speeds of single session between RMA and RM using 1, 2, 3, and 4 kbyte unit data are similar, 62.32ms, 62.65ms, 63.02ms, and 63.48ms, respectively. Likewise, those of 128 muliple sessions using 1, 2, 3, and 4 kbyte unit data are not much more time difference, 298.08ms, 302.21ms, 322.85ms, and 329.62ms, respectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.5
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• pp.29-38
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• 1985

In this paper we have designed and implemented in real time a simple, efficient and flexible AOPCM cosec using a high speed digital processor, NEC 7720. For ADPCM system, we have used an instantaneous adaptive quantizer and a first-order fixed predictor. The software for NEC 7720 has been developed and it was found that the NEC 7720 was capable of performing the entire ADPCAt algorithm for 4 channels in real time as optimizing the program. Computer simulation has born made to investigate a computational accuracr of NEC 7720 and to de-termine necessary parameters for a ADPCM codec. Real telephone speech, RC-shaped Gaussian noise and 1004 Hz tone signal were used for simulation. In simulation, the parameters werc optimized from the computed SNR and the informal listening test. The developed software was tested in real time operation using a hardware emulator for NEC 7720. It took a maximum 23.25$\mu$s to encode one sample and 113.5$\mu$s, including all the necessary 1/0 operations, to encode 4 channels. In the case of decoding process, it took 24.75$\mu$s to decode one sample and 119.5$\mu$s to decode 4 channels.

• Smart Structures and Systems
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• v.16 no.3
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• pp.383-399
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• 2015

Today, as railways increase their capacity and speeds, it is more important than ever to be completely aware of the state of vehicles fleet's condition to ensure the highest quality and safety standards, as well as being able to maintain the costs as low as possible. Operation of a modern, dynamic and efficient railway demands a real time, accurate and reliable evaluation of the infrastructure assets, including signal networks and diagnostic systems able to acquire functional parameters. In the conventional system, measurement data are reliably collected using coaxial wires for communication between sensors and the repository. As sensors grow in size, the cost of the monitoring system can grow. Recently, auto-powered wireless sensor has been considered as an alternative tool for economical and accurate realization of structural health monitoring system, being provided by the following essential features: on-board micro-processor, sensing capability, wireless communication, auto-powered battery, and low cost. In this work, an original harvester device is designed to supply wireless sensor system battery using train bogie energy. Piezoelectric materials have in here considered due to their established ability to directly convert applied strain energy into usable electric energy and their relatively simple modelling into an integrated system. The mechanical and electrical properties of the system are studied according to the project specifications. The numerical formulation is implemented with in-house code using commercial software tool and then experimentally validated through a proof of concept setup using an excitation signal by a real application scenario.

• Proceedings of the KSR Conference
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• 2009.05a
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• pp.860-865
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• 2009

This thesis deals with application of Windows CE for Embedded System and the development methode of "Speed Gate Controller Tester" taking advantage of development program. We can improve reliability, stability and convenience of maintenance work as use of "Speed Gate Controller Tester" which was developed and applied "Embedded System" We can provide customers with more qualified service naturally because of the higher rate of operation which makes people use more pleasant and comfortable subway facility. And also it is possible to manage processor, time schedule and hardware resource as application of Embedded System and Windows CE. Embedded System applied OS Windows CE makes it possible to develop other various products, another application of equipment and tester. Thus this paper treats problems the moment developed and the present condition, development process, field application results.

• Nuclear Engineering and Technology
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• v.44 no.4
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• pp.421-428
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• 2012

Analog instrument and control systems in nuclear power plants have recently been replaced with digital systems for safer and more efficient operation. Digital instrument and control systems have adopted various fault-tolerant techniques that help the system correctly and safely perform the specific required functions regardless of the presence of faults. Each fault-tolerant technique has a different inspection period, from real-time monitoring to monthly testing. The range covered by each faulttolerant technique is also different. The digital instrument and control system, therefore, adopts multiple barriers consisting of various fault-tolerant techniques to increase the total fault detection coverage. Even though these fault-tolerant techniques are adopted to ensure and improve the safety of a system, their effects on the system safety have not yet been properly considered in most probabilistic safety analysis models. Therefore, it is necessary to develop an evaluation method that can describe these features of digital instrument and control systems. Several issues must be considered in the fault coverage estimation of a digital instrument and control system, and two of these are addressed in this work. The first is to quantify the fault coverage of each fault-tolerant technique implemented in the system, and the second is to exclude the duplicated effect of fault-tolerant techniques implemented simultaneously at each level of the system's hierarchy, as a fault occurring in a system might be detected by one or more fault-tolerant techniques. For this work, a fault injection experiment was used to obtain the exact relations between faults and multiple barriers of faulttolerant techniques. This experiment was applied to a bistable processor of a reactor protection system.