• Spatial Information Research
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• v.10 no.1
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• pp.61-76
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• 2002

Mobile map services using PDA are prevailing because of the rapid developments of techniques of the internet and handhold devices recently. While the volume of spatial data is tremendous and the spatial operations are time-intensive, the PDA has small size memory and a low performance processor. Therefore, the spatial index for PDA should be small size and efficiently filter out the candidate objects of spatial operation as well. This paper proposes a spatial index far PDA called MHF(Multilevel Hashing File). The MHF has simple structure for storage efficiency and uses a hashing technique, which is direct search method, for search efficiency. This paper also designs a compression technique for MBR. which occupies almost 80% of index data in the two dimensional case. We call it HMBR. Although the HMBR technique reduces the MB\ulcorner size to almost a third, it shows good filtering efficiency because of no information loss by quantization in case of small objects that occupy a major portion. Our experimental tests show that the proposed MHF index using HMBR technique is appropriate for PDA in terms of the size of index, the Number of MBR comparisons, the filtering efficiency and the execution time of spatial operations.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.35 no.11
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• pp.1399-1406
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• 2011

The reducer of the mixer is one of the main parts of the processor used for water and wastewater treatment. In this study, an advanced reducer with a drywell structure was developed in order to prevent oil leakage during operation in the field. During the development of the advanced reducer prototype, a mockup, a metal mold, and a cast were made using CAD and a CNC machine. The structural safety of the reducer prototype's lower housing (drywell structure) was checked using the ALGOR commercial FEM analysis code, which yielded a von Mises stress of about 123 N/mm2, which is below the yield stress of 250 N/$mm^2$, and a natural frequency of about 650-700 Hz. In addition, the torque transmission efficiency for the advanced prototype was 95.87%, which is about 8% more than that found in a previous study, 88.45%, and the sound level was below 75 dB. Furthermore, no oil leakage or abnormal sound or vibration occurred. Therefore, an optimally designed advanced reducer prototype has been successfully developed.

• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.5
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• pp.215-225
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• 2020

Light detection and ranging (LiDAR) sensors detect the distance of the surrounding environment and objects. Conventional LiDAR sensors require a certain amount of a power because they detect objects by transmitting lasers at a regular interval depending on a constant resolution. The constant power consumption from operating multiple LiDAR sensors is detrimental to autonomous and electric vehicles using battery power. In this paper, we propose two algorithms that improve the inefficient power consumption during the constant operation of LiDAR sensors. LiDAR sensors with algorithms efficiently reduce the power consumption in two ways: (a) controlling the resolution to vary the laser transmission period (T_P) of a laser diode (LD) depending on the vehicle's speed and (b) reducing the static power consumption using a sleep mode depending on the surrounding environment. A proposed LiDAR sensor with a resolution control algorithm reduces the power consumption of the LD by 6.92% to 32.43% depending on the vehicle's speed, compared to the maximum number of laser transmissions (N_x·max). The sleep mode with a surrounding environment-sensing algorithm reduces the power consumption by 61.09%. The proposed LiDAR sensor has a risk factor for 4-cycles that does not detect objects in the sleep mode, but we consider it to be negligible because it immediately switches to an active mode when a change in surrounding conditions occurs. The proposed LiDAR sensor was tested on a commercial processor chip with the algorithm controlling the resolution according to the vehicle's speed and the surrounding environment.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.5
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• pp.1-6
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• 2016

Image rotation is one of main pre-processing step in image processing or image pattern recognition. It is implemented with rotation matrix multiplication. However it requires lots of floating point arithmetic operations and trigonometric function calculations, so it takes long execution time. We propose a new high speed image rotation algorithm without two major time-consuming operations. It use just 2 shear translation operations, so it is very fast. In addition, we apply a parallel computing technique with CUDA. CUDA is a massively parallel computing architecture using prevailed GPU recently. As GPU is a dedicated graphic processor, it is exellent for parallel processing of pixels. We compare the proposed algorithm with the conventional rotation one with various size images. Experimental results show that the proposed algorithm is superior to the conventional rotation ones.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.3
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• pp.117-124
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• 2002

A high speed data link capability is one of the critical factors in determining the performance of the spaceborne SAR system with high resolution because of the strict requirement for the real-time data transmission of the massive SAR data in a limited time of mission. In this paper, based on the data link model characterized by the spaceborne small SAR system, the high rate multi-channel data link module is designed including link storage, link processor, transmitter, and wide-angle antenna. The design results are presented with the performance analysis on the data link budget as well as the multi-mode data rate in association with the SAR imaging mode of operation from high resolution to the wide swath. The designed data link module can be effectively used for the spaceborne and airborne applications which requires to expand the high speed data link capability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.20-25
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• 2009

We propose hardware architecture of floating-point square root and inverse square root arithmetic units using lookup tables. They are used for lighting engines and shader processor for 3D graphic processing. The architecture is based on Taylor series expansion and consists of lookup tables and correction units so that the size of look-up tables are reduced. It can be applied to 32 bit floating point formats of IEEE-754 and reduced 24 bit floating point formats. The square root and inverse square root arithmetic units for 32 bit and 24 bit floating format number are designed as the proposed architecture. They can operation in a single cycle, and satisfy the precision of $10^{-5}$ required by OpenGL 1.x ES. They are designed using Verilog-HDL and the RTL codes are verified using an FPGA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.67-74
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• 2005

Crypto-systems have difficulties in designing hardware due to the various standards. We propose a programmable and configurable architecture for cryptography coprocessors to accommodate various crypto-systems. The proposed architecture has a 32 bit I/O interface and internal bus width, and consists of a programmable finite field arithmetic unit, an input/output unit, a register file, and a control unit. The crypto-system is determined by the micro-codes in memory of the control unit, and is configured by programming the micro-codes. The coprocessor has a modular structure so that the arithmetic unit can be replaced if a substitute has an appropriate 32 bit I/O interface. It can be used in many crypto-systems by re-programming the micro-codes for corresponding crypto-system or by replacing operation units. We implement an elliptic curve crypto-processor using the proposed architecture and compare it with other crypto-processors

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.12
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• pp.1678-1687
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• 2013

This paper describes a prototype of 3-phase 3.3kV/220V 6kVA modular semiconductor transformer developed in the lab for feasibility study. The developed prototype is composed of three single-phase units coupled in Y-connection. Each single-phase unit with a rating of 1.9kV/127V 2kVA consists of a high-voltage high-frequency resonant AC-DC converter, a low-voltage hybrid-switching DC-DC converter, and a low-voltage hybrid-switching DC-AC converter. Also each single-phase unit has two DSP controllers to control converter operation and to acquire monitoring data. Monitoring system was developed based on LabView by using CAN communication link between the DSP controller and PC. Through various experimental analyses it was verified that the prototype operates with proper performance under normal and sag condition. The system efficiency can be improved by adopting optimal design and replacing the IGBT switch with the SiC MOSFET switch. The developed prototype confirms a possibility to build a commercial high-voltage high-power semiconductor transformer by increasing the number of series-connected converter modules in high-voltage side and improving the performance of switching element.

• Journal of Korea Multimedia Society
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• v.13 no.1
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• pp.30-37
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• 2010

Many embedded real - lime systems have adopted processors supported with dynamic voltage scal-ing(DVS) recently. Power is one of the important metrics for Optimization in the design and operation of embedded real-time systems. We can save considerable energy by using slowdown of processor sup-ported with DVS. In this paper, we improved the previous algorithm at a point of view of time complexity to calculate task slowdown factors for an efficient energy consumption in embedded real-time systems with task synchronization. We grasped the properties of the previous algorithm having $O(n^{2})$ time complexity through mathematical analysis and s simulation. Using its properties we proposed the improved algorithms with O(nlogn) and O(n) time complexity which have the same performance as the previous algorithm has.

• The Journal of the Acoustical Society of Korea
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• v.19 no.4
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• pp.31-36
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• 2000

This paper describes the implementation and the evaluation of the speech recognition automatic exchange system. The system provides government or public offices, companies, educational institutions that are composed of large number of members and parts with exchange service using speech recognition technology. The recognizer of the system is a Speaker-Independent, Isolated-word, Flexible-Vocabulary recognizer based on SCHMM(Semi-Continuous Hidden Markov Model). For real-time implementation, DSP TMS320C32 made in Texas Instrument Inc. is used. The system operating terminal including the diagnosis of speech recognition DSP and the alternation of speech recognition candidates makes operation easy. In this experiment, 8 speakers pronounced words of 1,300 vocabulary related to automatic exchange system over wire telephone network and the recognition system achieved 91.5% of word accuracy.