• Journal of Biosystems Engineering
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• v.26 no.3
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• pp.287-294
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• 2001

The geometrical and physical properties of red peppers were studied for proper design of a red pepper processor. Mass, volume, roundness and compactness of red peppers were calculated from digital images. They were compared with real data and the relations of them were suggested. Roundness of red peppers was ranged from 0.2 to 0.5 and the average value was 0.349. Compactness of red peppers was ranged from 25 to 50 and the average value was 37.1. The regression equations to calculate the volume and mass of red pepper were obtained as y$\_$v/$\_$=/0.553$\varkappa$$_1$+1.441$\varkappa$$_2$-1.013$\varkappa$$_3$(R=0.95) and y$\_$m/=0.252$\varkappa$$_1$+0.938$\varkappa$$_2$-0.499$\varkappa$$_3$-1.5112 (R=0.93), y$\_$v/:volume(㎤), y$\_$m/:mass(g), $\varkappa$$_1$: perimeter(cm), $\varkappa$$_2$: area(㎠), $\varkappa$$_3$: length of major axis(cm), respectively. The direction for aligning the red pepper in a machine processing was easily and perfectly recognized. The response time for digital image processing has to be reduced for more efficient operation. HSI and YIQ values could be useful for recognizing the red pepper from background.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.123-130
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• 2016

In this paper, a high-performance arithmetic unit which can efficiently accelerate a number of algorithms for multimedia application was designed. The 3-stage pipelined arithmetic unit can execute 38 operations for complex and fixed-point data by using efficient configuration for four 16-bit by 16-bit multipliers, new sign extension method for carry-save data, and correction constant scheme to eliminate sign-extension in compression operation of multiple partial multiplication results. The arithmetic unit has about 300-MHz operating frequency and about 37,000 gates on 45nm CMOS technology and its estimated performance is 300 MCOPS(Million Complex Operations Per Second). Because the arithmetic unit has high processing rate and supports a number of operations dedicated to various applications, it can be efficiently applicable to multimedia processors.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.54 no.8
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• pp.375-387
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• 2005

This paper presents an application of parallel Genetic Algorithm-Tabu Search (GA-TS) algorithm to search an optimal solution of a service restoration in distribution systems. The main objective of service restoration of distribution systems is, when a fault or overload occurs, to restore as much load as possible by transferring the do-energized load in the out of service area via network reconfiguration to the appropriate adjacent feeders at minimum operational cost without violating operating constraints, which is a combinatorial optimization problem. This problem has many constraints with many local minima to solve the optimal switch position. This paper develops parallel GA-TS algorithm for service restoration of distribution systems. In parallel GA-TS, GA operators are executed for each processor. To prevent solutions of low fitness from appearing in the next generation, strings below the average fitness are saved in the tabu list. If best fitness of the GA is not changed for several generations, TS operators are executed for the upper $10\%$ of the population to enhance the local searching capabilities. With migration operation, best string of each node is transferred to the neighboring node after predetermined iterations are executed. For parallel computing, we developed a PC cluster system consists of 8 PCs. Each PC employs the 2 GHz Pentium IV CPU and is connected with others through ethernet switch based fast ethernet. To show the validity of the proposed method, proposed algorithm has been tested with a practical distribution system in Korea. From the simulation results, we can find that the proposed algorithm is efficient for the distribution system service restoration in terms of the solution quality, speedup, efficiency and computation time.

• Journal of Energy Engineering
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• v.19 no.2
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• pp.128-135
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• 2010

This paper introduces step by step procedures for the fabrication and operation of an embedded solar tracker. The system presented consists of application software, compactRIO, C-series interface module, analogue input module, step drive, step motor, feedback devices and other accessories to support its functional stability. CompactRIO that has a real-tim processor allows the solar tracker to be a stand-alone real time system which operates automatically without any external control. An astronomical method and an optical method were used for a high-precision solar tracker. CdS sensors are used to constantly generate feedback signals to the controller, which allow a solar tracker to track the sun even under adverse conditions. The database of solar position and sunrise and sunset time was compared with those of those of the Astronomical Applications Department of the U.S. Naval Observatory. The results presented here clearly demonstrate the high-accuracy of the present system in solar tracking, which are applicable to many existing solar systems.

• Journal of Korea Multimedia Society
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• v.9 no.4
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• pp.388-400
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• 2006

There are wireless location acquisition technique, LBS platform technique, and LBS application technique in the important technical elements of the LBS. In this paper, we design a location data management system which is the core base technique of the important technical elements of the LBS. The proposed system consist of an application interface of LBS, a query processor of application. service, a location estimator of the moving objects, a location information manager, a real-time data receiver, and a database of location data. This system manages efficiently the location change information of the moving objects using the database technique, suggests some useful inform to the users of LBS, and supports operation and facility of location estimation to process continuous location data of the moving objects. On the basis of location data triggering, this system supplements the problem of the related location data management systems to complement the loss of location data in the environment of real-time.

• The Journal of the Korea Contents Association
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• v.9 no.11
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• pp.90-99
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• 2009

This paper presents the implementation of RFID EPC global network educational system based on using 900MHz air interface between the reader and the active tag. The software of reader and the active tag is developed on embedded environment, and the software of PC controlling the reader is based on window OS operated as the server. The ATmega128 VLSI chip is used for the processor of the reader and the active tag. As the development environment, AVR compiler is used for the reader and the active tag of which the programming language is C. The visual C++language of the visual studio on the PC activated as the server is used for development language. Main functions of this system are to control tag containing EPC global Data by PC through the reader, to obtain information of tag through the internet and to read/write data on tag memory. Finally the data written from the active tag's memory is sent to the PC via the reader as "read" operation and compare the received data with one already sent to the tag. Software implementation of 900MHz EPC global RFID educational system is done on the basis of these functions.

• Journal of Intelligence and Information Systems
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• v.15 no.4
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• pp.213-224
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• 2009

This paper describes a real-time scheduling system re-construction project for automated manufacturing at a 300mm wafer fab of Korean semiconductor manufacturing company. During executing this project, for each main operation such as clean, diffusion, deposition, photolithography, and metallization, each adopted scheduling algorithm was developed, and then those were implemented in a real-time scheduling system. In this paper, we focus on the scheduling algorithms and real-time scheduling system for clean and diffusion operations, that is, a serial-process block with the constraint of limited queue time and batch processors. After this project was completed, the automated manufacturing utilizations of clean and diffusion operations became around 91% and 83% respectively, which were about 50% and 10% at the beginning of this project. The automated manufacturing system reduces direct operating costs, increased throughput on the equipments, and suggests continuous and uninterrupted processings.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.499-503
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• 2000

The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

• Journal of Korea Multimedia Society
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• v.14 no.3
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• pp.368-377
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• 2011

This paper explains the hardware structure of SURF(Speeded Up Robust Feature) based feature point extractor and its FPGA verification result. SURF algorithm produces novel scale- and rotation-invariant feature point and descriptor which can be used for object recognition, creation of panorama image, 3D Image restoration. But the feature point extraction processing takes approximately 7,200msec for VGA-resolution in embedded environment using ARM11(667Mhz) processor and 128Mbytes DDR memory, hence its real-time operation is not guaranteed. We analyzed integral image memory access pattern which is a key component of SURF algorithm to reduce memory access and memory usage to operate in c real-time. We assure feature extraction that using a Vertex-5 FPGA gives 60frame/sec of VGA image at 100Mhz.

• Journal of Advanced Navigation Technology
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• v.21 no.6
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• pp.638-642
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• 2017

FOD is a generic term for substances with potential threats that can pose a fatal risk to aircraft. Therefore, FOD should be noted in all areas of the airport. Especially, the method of detecting and collecting FOD in runway and aircraft movements is very low efficiency and economical efficiency of airport operation, so it is essential to develop FOD automatic detection system suitable for domestic environment. As part of the aviation safety technology development project, the development of an automatic detection system for foreign matter in the moving area of the aircraft inside the airport is underway. In this paper, it is confirmed that EO / IR camera is used for detection of foreign objects at Taean Airfield of Hanseo University. EO camera is used during the day and IR camera is used at night.