• Title/Summary/Keyword: Operation Processor

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Implementation of Low Power PostPC Terminal (저전력 PostPC 통합 단말기 구현)

  • Kim, Yong-Ho;Cho, Soo-Hyung;Kim, Dae-Hwan
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.1027-1028
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    • 2006
  • A case study in low-power PostPC Platform is presented. We introduce an S3C2460 Mobile SoC Processor and Implementation of Embedded Linux on out platform. This Processor is designed to Multimedia & Telecommunication Applications. We focuse on the verification of S3C2460 Processor and operation of Embedded Linux OS on it.

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A Study On the Design of Mixed Radix Converter using Partitioned Residues. (분할 잉여수를 사용한 혼합기수변환기 설계에 관한 연구)

  • 김용성
    • The Journal of Information Technology
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    • v.4 no.4
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    • pp.51-63
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    • 2001
  • Residue Number System has carry free operation and parallelism each modulus, So it is used for special purpose processor such as Digital Signal Processing and Neuron Processor. Magnitude comparison and sign detection are in need of Mixed Radix Conversion, and these operations are impediment to improve the operation speed. So in this Paper, MRC(Mixed Radix Converter) is designed using modified partitioned residue to speed up the operation of MRC, so it has progressed maximum twice operation time but increased the size of converter comparison to other converter.

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A design of Floating Point Arithmetic Unit for Geometry Operation of Mobile 3D Graphic Processor (모바일 3D 그래픽 프로세서의 지오메트리 연산을 위한 부동 소수점 연산기 구현)

  • Lee, Jee-Myong;Lee, Chan-Ho
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.711-714
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    • 2005
  • We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.

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On-Chip Debug Architecture for Multicore Processor

  • Park, Hyeong-Bae;Xu, Jing-Zhe;Kim, Kil-Hyun;Park, Ju-Sung
    • ETRI Journal
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    • v.34 no.1
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    • pp.44-54
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    • 2012
  • Because of the intrinsic lack of internal-system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on-chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run-stop-type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG-based scanning operation. We apply this on-chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.

Analysis of MX-TM CFAR Processors in Radar Detection (레이다 검파에서의 MX-TM CFAR 처리기들에 대한 성능 분석)

  • 김재곤;조규홍;김응태;이동윤;송익호;김형명
    • Proceedings of the Korean Institute of Communication Sciences Conference
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    • 1991.10a
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    • pp.92-95
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    • 1991
  • Constant false alarm rate(CFAR) processors are useful for detecting radar targets in background for which all parameters in the statistical distribution are not known and may be nonstationary. The well known "cell averging" (CA) CFAR processor is known to yield best performance in homogeneous case, but exhibits severe performance in the presence of an interfering target in the reference window or/and in the region of clutter edges. The "order statistics"(OS) CFAR processor is known to have a good performance above two nonhomogeneous cases. The modified OS-CFAR processor, known as "trimmed mean"(TM) CFAR processor performs somewhat better than the OS-CFAR processor by judiciously trimming the ordered samples. This paper proposes and analyzes the performance of a new CFAR processor called the "maximum trimmed mean"(MX-TM) CFAR processor combining the "greatest of"(GO) CFAR and TM-CFAR processors. The MAX operation is included to control false alarms at clutter edges. Our analyses show that the proposed CFAR processor has similar performance TM- and OS-CFAR processors in homogeneous case and in the precence of interfering targets, but can control the false rate in clutter edges. Simulation results are presented to demonstrate the qualitative effects of various CFAR processors in nonhomogeneous clutter environments.

PASC Processor Architecture for Enhanced Loop Execution (루프를 효과적으로 처리하는 PASC 프로세서 구조)

  • Ji, Seung-Hyeon;Park, No-Gwang;Jeon, Jung-Nam;Kim, Seok-Il
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.5
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    • pp.1225-1240
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    • 1999
  • This paper proposes PASC(PArtitioned SCHeduler) processor architecture that equips with a number of functional unit and an individual scheduler paris. Every scheduler of the PASC processor can determine whether a unit instruction can be issued to the associated functional unit or it is to be waited until next cycle caused by a resource collision or data dependencies. In the PASC processor, only the functional unit with a resource collision or data dependencies waits by executing a NOP(No OPeration) instruction and the other functional units execute their own instructions. Therefore we can expect the code compaction effect on the PASC processor. Thus, the last instruction of a loop at certain iteration and the very first instruction of the loop at the next iteration can be scheduled simultaneously if the two instructions do not incur any resource collision or data dependencies. Therefore, we can expect that such two instructions without any resource collision and data dependencies are packed into the same very long instruction word and thus, the two instructions are executed concurrently at run time. As a result, we can shorten execution cycles of a loop comparing to the execution of the loop on a traditional VLIW or SVLIW processor architecture. Simulation result also promises faster execution of loops on a PASC processor architecture than those on a VLIW and SVLIW processor architecture.

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A study on the Description and Simulation of a SIC using a VHDL (VHDL을 이용한 SIC의 기술과 시뮬레이션)

  • Park, Doo-Youl
    • Journal of the Korea Computer Industry Society
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    • v.9 no.4
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    • pp.157-170
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    • 2008
  • In this paper, we described the Parwan(PAR-1) CPU that be developed as a reduced processor at Messachusetts Microelectronics Center using a VHDL at the behavioral level and then described by connecting CPU components at the dataflow level. Finally, we used Test-bench method to simulate and verify execution of CPU processor that was designed using a VHDL <중략> Here, Presented method was to enable information exchange of design and representation of operation were very exact and simple. Also, a documentation of design was available and it was easy that verify a operation of designed processor. The behavioral description of VHDL aids designer as we verify our understanding of the designed system, thus the dataflow description can be used to verify the bussing and register structure of the design.

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PEMFC Operation Connected with Methanol Reformer System

  • Lee, Jung-Hyun;Park, Sang-Sun;Shul, Yong-Gun;Park, Jong-Man;Kim, Dong-Hyun;Kim, Ha-Suck;Yoo, Seung-Eul
    • Carbon letters
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    • v.9 no.4
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    • pp.303-307
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    • 2008
  • The studies on integrated operation of fuel cell with fuel processor are very essential prior to its commercialization. In this study, Polymer Electrolyte Membrane Fuel Cell (PEMFC) was operated with a fuel processor, which is mainly composed of two parts, methanol steam reforming reaction and preferential oxidation (PROX). In fuel processor, ICI 33-5 (CuO 50%, ZnO 33%, $Al_2O_3$ 8%, BET surface area: $66\;m^2g^{-1}$) catalyst and CuO-$CeO_2$ catalyst were used for methanol steam reforming, preferential oxidation (PROX) respectively. PEMFC was operated by hydrogen fuel generated from fuel processor. The resulting gas from PROX reactor is used to operate PEMFC equipped with our prepared anode and cathode catalyst. PtRu/C catalyst gives more tolerance to CO.

Energy-Efficient DNN Processor on Embedded Systems for Spontaneous Human-Robot Interaction

  • Kim, Changhyeon;Yoo, Hoi-Jun
    • Journal of Semiconductor Engineering
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    • v.2 no.2
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    • pp.130-135
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    • 2021
  • Recently, deep neural networks (DNNs) are actively used for action control so that an autonomous system, such as the robot, can perform human-like behaviors and operations. Unlike recognition tasks, the real-time operation is essential in action control, and it is too slow to use remote learning on a server communicating through a network. New learning techniques, such as reinforcement learning (RL), are needed to determine and select the correct robot behavior locally. In this paper, we propose an energy-efficient DNN processor with a LUT-based processing engine and near-zero skipper. A CNN-based facial emotion recognition and an RNN-based emotional dialogue generation model is integrated for natural HRI system and tested with the proposed processor. It supports 1b to 16b variable weight bit precision with and 57.6% and 28.5% lower energy consumption than conventional MAC arithmetic units for 1b and 16b weight precision. Also, the near-zero skipper reduces 36% of MAC operation and consumes 28% lower energy consumption for facial emotion recognition tasks. Implemented in 65nm CMOS process, the proposed processor occupies 1784×1784 um2 areas and dissipates 0.28 mW and 34.4 mW at 1fps and 30fps facial emotion recognition tasks.

NC Code Post-Processor Considering Metal Removal Rate (절삭부하 예측을 통한 NC코드 후처리시스템)

  • 이기우;노상도;신동목;한형상
    • Journal of the Korean Society for Precision Engineering
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    • v.17 no.5
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    • pp.116-123
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    • 2000
  • This paper presents an NC code post-processor that adjusts feedrates to keep the variation of metal removal rate along the tool paths minimum. Metal removal rate is estimated by virtually machining the part, whose surface model is built from a series of NC codes defined in operation plan, with cutting-tool-assembly models, whose geometry are defined in a machining database. The NC code post-processor modifies the feedrates by the adjustment rules, which are based on the machining knowledge for effective machining. This paper illustrates a procedure fur grouping machining conditions and we also show how to determine an adjustment rule for a machining-condition group. An example part was machined and it shows that the variation of cutting force was dramatically reduced after applying the NC code post-processor. The NC code post-processor is expected to increase productivity while maintaining the quality of the machined part.

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