• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2093-2099
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• 2016

This paper describes a design of crypto-processor that supports multiple block cipher algorithms of PRESENT, ARIA, and AES. The crypto-processor integrates three cores that are PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES), and AES-16b. The PRmo core implementing 64-bit block cipher PRESENT supports key length 80-bit and 128-bit, and four modes of operation including ECB, CBC, OFB, and CTR. The AR_AS core supporting key length 128-bit and 256-bit integrates two 128-bit block ciphers ARIA and AES into a single data-path by utilizing resource sharing technique. The AES-16b core supporting key length 128-bit implements AES with a reduced data-path of 16-bit for minimizing hardware. Each crypto-core contains its own on-the-fly key scheduler, and consecutive blocks of plaintext/ciphertext can be processed without reloading key. The crypto-processor was verified by FPGA implementation. The crypto-processor implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,500 gate equivalents (GEs), and it can operate with 55 MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1185-1194
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• 1997

It is necessary to control the frame memory to capture, edit and display images. This paper presents the free-scale image capture processor size of which is user-defined, compared to the conventional image capture processor size of which is fixed 1/2, 1/4 and full size. User-defined scale data is fed into this system, which generates the gating pulses and gates the inputted image data. This system also controls the 4M DRAM instead of frame meamory. And stored gated image data are displayed on the TV monitor. We designed the scalable image capture parts and DRAM controller with ACTEL FPGAs, simulated the circuits with Viewlogic and fusing ACTEL A1020B chips. We confirmed the whole operation with beadboard which composed of "Philips TV Chipset" and designed FPGA chips.PGA chips.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.923-928
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• 1990

This paper describes the design and implementation of a real-time, high-precision vision system and its application to SMT(surface mounting technology) automation. The vision system employs a 32 bit MC68030 as a main processor, and consists of image acquisition unit. DSP56001 DSP based vision processor, and several algorithmically dedicated hardware modules. The image acquisition unit provides 512*480*8 bit image for high-precision vision tasks. The DSP vision processor and hardware modules, such as histogram extractor and feature extractor, are designed for a real-time excution of vision algorithms. Especially, the implementation of multi-processing architecture based on DSP vision processors allows us to employ more sophisticated and flexible vision algorithms for real-time operation. The developed vision system is combined with an Adept Robot system to form a complete SMD system. It has been found that the vision guided SMD assembly system is able to provide a satisfactory performance for SND automation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.3
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• pp.11-23
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• 1995

In this paper, a parallel pipelined processor model which acts as a small VLIW processor architecture and a scheduling algorithm for extracting instruction-level parallelism on this architecture are proposed. The proposed model has a dual-instruction mode which has maximum 4 basic operations being executed in parallel. By combining these basic operations, variable instruction set can be designed for various applications. The scheduling algorithm schedules basic operations for parallel execution and removes pipeline hazards by examining data dependency and resource conflict relations. In order to examine operation and evaluate the performance,a C compiler and a simulator are developed. By simulating various test programs with the compiler and the simulator, the characteristics and the performance result of the proposed architecture are measured.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.263-264
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• 2007

In this paper, an efficient SAD(Sum of Absolute Differences) processor structure for motion estimation of 0.264 is proposed. SAD processors are commonly used both in full search methods for motion estimation or in fast search methods for motion estimation. Proposed structure consists of SAD calculator block, combinator block, and minimum value calculator block. Especially, proposed structure is simplified by using Distributed Arithmetic for addition operation. The Verilog-HDL(Hard Description Language) coding and FPGA implementation results for the proposed structure show 39% and 32% gate count reduction comparison with those of the conventional structure, respectively. Due to its efficient processing scheme, the proposed SAD processor structure can be widely used in size dominant H.264 chip.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.715-722
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• 2010

This paper describes a hardware design of hash function processor which implements Korean Hash Algorithm Standard HAS-160. The HAS-160 processor compresses a message with arbitrary lengths into a hash code with a fixed length of 160-bit. To achieve high-speed operation with small-area, arithmetic operation for step-operation is implemented by using a hybrid structure of 5:3 and 3:2 carry-save adders and carry-select adder. It computes a 160-bit hash code from a message block of 512 bits in 82 clock cycles, and has 312 Mbps throughput at 50 MHz@3.3-V clock frequency. The designed HAS-160 processor is verified by FPGA implementation, and it has 17,600 gates on a layout area of about $1\;mm^2$ using a 0.35-${\mu}m$ CMOS cell library.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2333-2340
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• 2016

A LEA (Lightweight Encryption Algorithm) crypto-processor was designed, which supports three master key lengths of 128/ 192/256-bit, ECB and CTR modes of operation. To achieve high throughput rate, the round transformation block was designed with 128 bits datapath and a pipelined structure of 16 stages. Encryption/decryption is carried out through 12/14/16 pipelined stages according to the master key length, and each pipelined stage performs round transformation twice. The key scheduler block was optimized to share hardware resources that are required for encryption, decryption, and three master key lengths. The round keys generated by key scheduler are stored in 32 round key registers, and are repeatedly used in round transformation until master key is updated. The pipelined LEA processor was verified by FPGA implementation, and the estimated performance is about 8.3 Gbps at the maximum clock frequency of 130 MHz.

• Journal of IKEEE
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• v.22 no.2
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• pp.233-241
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• 2018

This paper describes a lightweight implementation of a cryptographic processor supporting GCM (Galois/Counter Mode) authenticated encryption (AE) that is based on the two block cipher algorithms of ARIA and AES. It also provides five modes of operation (ECB, CBC, OFB, CFB, CTR) for confidentiality as well as the key lengths of 128-bit and 256-bit. The ARIA and AES are integrated into a single hardware structure, which is based on their algorithm characteristics, and a $128{\times}12-b$ partially parallel GF (Galois field) multiplier is adopted to efficiently perform concurrent processing of CTR encryption and GHASH operation to achieve overall performance optimization. The hardware operation of the ARIA/AES-GCM AE processor was verified by FPGA implementation, and it occupied 60,800 gate equivalents (GEs) with a 180 nm CMOS cell library. The estimated throughput with the maximum clock frequency of 95 MHz are 1,105 Mbps and 810 Mbps in AES mode, 935 Mbps and 715 Mbps in ARIA mode, and 138~184 Mbps in GCM AE mode according to the key length.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.8 s.251
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• pp.731-740
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• 2006

The solid oxide fuel cell (SOFC) is expected to be a candidate for distributed power sources in the next generation, due to its high efficiency and high-temperature waste heat utilization. In this study, the 5-cell SOFC stack was operated with pure hydrogen or reformed gas at anode side and air at cathode side. When stack was operated with diesel and methane ATR reformer, the influence of the $H_2O/C,\;O_2/C$ and GHSV on performance of stacks have been investigated. The result shows that the cell voltage was decreased with the increase of $H_2O/C$ and $O_2/C$ due to the partial pressure of fuel and water, and cell voltage was more sensitive to $O_2/C$ than $H_2O/C$. Next, the dynamic model of SOFC system included with ATR reformer was established and compared with experimental data. Based on dynamic model, the operation strategy to optimize SOFC-Reformer system was suggested and simulated.