• Proceedings of the Korea Information Processing Society Conference
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• 2008.11a
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• pp.885-888
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• 2008

낸드(NAND) 플래시 메모리와 노어(NOR) 플래시 메모리의 장점을 결합시킨 원낸드(OneNAND) 플래시 메모리가 개발되면서 메모리의 시장에 큰 변화가 왔다. 그러나 기존의 낸드 플래시 메모리에서 사용되던 메모리 관리 기법이 그대로 원낸드 플래시 메모리에서 사용됨에 따라 원낸드 플래시 메모리만의 장점을 활용하지 못하고 있다. 본 논문에서는 기존의 메모리 관리 기법을 원낸드 플래시 메모리에 적합한 형태로 개선하였다. 제안 기법은 XIP 기능과 새로운 버퍼 관리 방법을 활용하여 원낸드 플래시 메모리의 성능을 최대한 이끌어 낸다. 그 결과 시스템의 전체적인 수행속도를 향상시킬 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.360-369
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• 2012

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

• Journal of KIISE
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• v.43 no.4
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• pp.411-418
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• 2016

In recent times, NAND flash memory has become widely used as secondary storage for computing devices. Accordingly, to take advantage of NAND flash memory, new file systems have been actively studied and proposed. The performance of these file systems is generally measured with benchmark tools. However, since benchmark tools are executed by software simulation methods, many researchers get non-uniform benchmark results depending on the system environments. In this paper, we use Filebench, one of the most popular and representative benchmark tools, to analyze benchmark results and study the reasons why the benchmark result variations occur. Our experimental results show the differences in benchmark results depending on the system environments. In addition, this study substantiates the fact that system performance is affected mainly by background I/O requests and fsync operations.

• The Journal of the Korea Contents Association
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• v.16 no.3
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• pp.91-101
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• 2016

This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.

• Journal of Internet of Things and Convergence
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• v.10 no.3
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• pp.19-24
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• 2024

Recent advances in large-scale data processing technologies such as big data, cloud computing, and artificial intelligence have increased the demand for high-performance storage devices in data centers and enterprise environments. In particular, the fast data response speed of storage devices is a key factor that determines the overall system performance. Solid state drives (SSDs) based on the Non-Volatile Memory Express (NVMe) interface are gaining traction, but new bottlenecks are emerging in the process of handling large data input and output requests from multiple hosts simultaneously. SSDs typically process host requests by sequentially stacking them in an internal queue. When long transfer length requests are processed first, shorter requests wait longer, increasing the average response time. To solve this problem, data transfer timeout and data partitioning methods have been proposed, but they do not provide a fundamental solution. In this paper, we propose a dual queue based scheduling scheme (DQBS), which manages the data transfer order based on the request order in one queue and the transfer length in the other queue. Then, the request time and transmission length are comprehensively considered to determine the efficient data transmission order. This enables the balanced processing of long and short requests, thus reducing the overall average response time. The simulation results show that the proposed method outperforms the existing sequential processing method. This study presents a scheduling technique that maximizes data transfer efficiency in a high-performance SSD environment, which is expected to contribute to the development of next-generation high-performance storage systems

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.122-122
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• 2008

Recently, Metal/Alumina/Silicon-Nitride/Silicon-Oxide/Silicon (MANOS) structures are one of the most attractive candidates to realize vertical scaling of high-density NAND flash memory [1]. However, as ANO layers are miniaturized, negative and positive bias temperature instability (NBTI/PBTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density increase, ${\Delta}D_{it}$, the gate leakage current, ${\Delta}I_G$. and the retention characteristics, in MONOS capacitors, becomes an important issue in terms of reliability. It is well known that tunnel oxide degradation is a result of the oxide and interfacial traps generation during FN (Fowler-Nordheim) stress [2]. Because the bias temperature stress causes an increase of both interfacial-traps and fixed oxide charge could be a factor, witch can degrade device reliability during the program and erase operation. However, few studies on NBTI/PBTI have been conducted on improving the reliability of MONOS devices. In this work, we investigate the effect of post-annealing gas on bias temperature instability (BTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density shift, ${\Delta}I_G$ retention characteristics, and the gate leakage current characteristics of MANOS capacitors. MANOS samples annealed at $950^{\circ}C$ for 30 s by a rapid thermal process were treated via additional annealing in a furnace, using annealing gases $N_2$ and $N_2-H_2$ (2 % hydrogen and 98 % nitrogen mixture gases) at $450^{\circ}C$ for 30 min. MANOS samples annealed in $N_2-H_2$ ambient had the lowest flat band voltage shift, ${\Delta}V_{FB}$ = 1.09/0.63 V at the program/erase state, and the good retention characteristics, 123/84 mV/decade at the program/erase state more than the sample annealed at $N_2$ ambient.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.546-546
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• 2008

Copper (Cu) Chemical mechanical polishing (CMP) has been an essential process for Cu wifing of DRAM and NAND flash memory beyond 45nm. Copper has been employed as ideal material for interconnect and metal line due to the low resistivity and high resistant to electro-migration. Damascene process is currently used in conjunction with CMP in the fabrication of multi-level copper interconnects for advanced logic and memory devices. Cu CMP involves removal of material by the combination of chemical and mechanical action. Chemicals in slurry aid in material removal by modifying the surface film while abrasion between the particles, pad, and the modified film facilitates mechanical removal. In our research, we emphasized on the role of chemical effect of slurry on Cu CMP, especially on the effect of amine functional group on removal rate selectivity between Cu and Tantalum-nitride (TaN) film. We investigated the two different kinds of complexing agent both with amine functional group. On the one hand, Polyacrylamide as a polymer affected the stability of abrasive, viscosity of slurry and the corrosion current of copper film especially at high concentration. At higher concentration, the aggregation of abrasive particles was suppressed by the steric effect of PAM, thus showed higher fraction of small particle distribution. It also showed a fluctuation behavior of the viscosity of slurry at high shear rate due to transformation of polymer chain. Also, because of forming thick passivation layer on the surface of Cu film, the diffusion of oxidant to the Cu surface was inhibited; therefore, the corrosion current with 0.7wt% PAM was smaller than that without PAM. the polishing rate of Cu film slightly increased up to 0.3wt%, then decreased with increasing of PAM concentration. On the contrary, the polishing rate of TaN film was strongly suppressed and saturated with increasing of PAM concentration at 0.3wt%. We also studied the electrostatic interaction between abrasive particle and Cu/TaN film with different PAM concentration. On the other hand, amino-methyl-propanol (AMP) as a single molecule does not affect the stability, rheological and corrosion behavior of the slurry as the polymer PAM. The polishing behavior of TaN film and selectivity with AMP appeared the similar trend to the slurry with PAM. The polishing behavior of Cu film with AMP, however, was quite different with that of PAM. We assume this difference was originated from different compactness of surface passivation layer on the Cu film under the same concentration due to the different molecular weight of PAM and AMP.