• Title/Summary/Keyword: One-chip processor

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Developement of IC Mark Checking System for IC Inspection Automation (반도체 소자(IC)의 검사 자동화를 위한 IC 표면의 마크 검사시스템 개발)

  • Bien, Zeung-Nam;You, Bum-Jae;Han, Dong-Il;Oh, Sang-Rok;Kim, Jung-Duck;Ha, Kyung-Ho
    • Proceedings of the KIEE Conference
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    • 1990.07a
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    • pp.471-474
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    • 1990
  • In this paper, a vision-based inspection algorithm for checking mark quality on an integrated chip(IC) is proposed. In order to reduce the processing time for inspection, we are implemented image arithmetic unit and binary image projection processor in hardware. By adopting the hardwares, the processing time becomes less one sixth of that in case of using software only.

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Energy Consumption Evaluation for Two-Level Cache with Non-Volatile Memory Targeting Mobile Processors

  • Matsuno, Shota;Togawa, Masashi;Yanagisawa, Masao;Kimura, Shinji;Sugibayashi, Tadahiko;Togawa, Nozomu
    • IEIE Transactions on Smart Processing and Computing
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    • v.2 no.4
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    • pp.226-239
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    • 2013
  • A number of systems have several on-chip memories with cache memory being one of them. Conventional cache memory consists of SRAM but the ratio of static energy to the total energy of the memory architecture becomes larger as the leakage power of traditional SRAM increases. Spin-Torque Transfer RAM (STT-RAM), which is a variety of Non-Volatile Memory (NVM), has many advantages over SRAM, such as high density, low leakage power, and non-volatility, but it consumes too much writing energy. This study evaluated a wide range of energy consumptions of a two-level cache using NVM partially on a mobile processor. Through a number of experimental evaluations, it was confirmed that the use of NVM partially in the two-level cache effectively reduces energy consumption significantly.

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Implementation of a Fieldbus System Based on EIA-709.1 Control Network Protocol (EIA-709.1 Control Network Protocol을 이용한 필드버스 시스템 구현)

  • Park, Byoung-Wook;Kim, Jung-Sub;Lee, Chang-Hee;Kim, Jong-Bae;Lim, Kye-Young
    • Journal of Institute of Control, Robotics and Systems
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    • v.6 no.7
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    • pp.594-601
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    • 2000
  • EIA-709.1 Control Network Protocol is the basic protocol of LonWorks systems that is emerg-ing as a fieldbus device. In this paper the protocol is implemented by using VHDL with FPGA and C program on an Intel 8051 processor. The protocol from the physical layer to the network layer of EIA-709.1 is im-plemented in a hardware level,. So it decreases the load of the CPU for implementing the protocol. We verify the commercial feasibility of the hardware through the communication test with Neuron Chip. based on EIA-709.1 protocol which is used in industrial fields. The developed protocol based on FPGA becomes one of IP can be applicable to various industrial field because it is implemented by VHDL.

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Design of Simple Controller for Minicar BLDC Motor Based on Low Cost Microprocessor

  • Tao, Yu;Song, Doo-Young;Lei, Zhang;Park, Sung-Jun;Jung, Tae-Uk;Kim, Cheul-U
    • Proceedings of the KIPE Conference
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    • 2007.07a
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    • pp.7-9
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    • 2007
  • If used to drive the minicar, the BLDC Motor has advantages of weightless, efficient, small-size and credibleness. In this paper at first the position detecting method for BLDC was introduced, secondly the simulation of control algorithm was done and at last the prototype controller based one chip processor MEGA48 was fabricated. The controller proposed has characteristic of cheap cost, reliable performance and totally meeting demands of minicar control.

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BLDC Motor Control Algorithm for Industrial Applications Using a General Purpose Processor

  • Kim, Nam-Hun;Yang, Oh;Kim, Min-Huei
    • Journal of Power Electronics
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    • v.7 no.2
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    • pp.132-139
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    • 2007
  • Electrical motors are an integral part of industrial plants with no less than 5 billion motors built world wide every year. The demand for low-cost brushless DC (BLDC) motors has increased in industrial applications. This paper presents a BLDC motor control algorithm for low-cost motor drive applications using general purpose microcontrollers which have only one on-chip timer. This paper describes how to realize pulse width modulation (PWM) signals with general input/output (I/O) ports to control a three-phase permanent magnet brushless DC motor using the timer interrupt on MSP430F1232.

MEM Temperature and Humidity Network Sensor for Wire and Wireless Network (유무선 통신용 MEMS 온습도 네트워크 센서)

  • Jung, Woo-Chul;Cha, Boo-Sang
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.06a
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    • pp.360-361
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    • 2006
  • This paper describes a wire and wireless network sensor for temperature and humidity measurements. The network sensor comprises PLC(Power Line Communication) and RF transmitter(433MHz) for acquiring an internal (on-board) sensor signal, and measured data is transmitted to a main processing unit. The network sensor module is consist of MEMS sensor, 10-bit A/D converter, pre-amp., gain-amp., ADUC812 one chip processor and PLC/RF transmitting unit. The temperature and humidity sensor is based on MEMS piezoelectric membrane structure and is implemented by using dual function sensor for smart home and smart building.

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3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • Lee, Kang-Wook
    • Journal of the Microelectronics and Packaging Society
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    • v.22 no.2
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

A VLSI Architecture of Systolic Array for FET Computation (고속 퓨리어 변환 연산용 VLSI 시스토릭 어레이 아키텍춰)

  • 신경욱;최병윤;이문기
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.9
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    • pp.1115-1124
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    • 1988
  • A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

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Fault Detection in the Two-for-One Twister

  • Park, Ho-Cheol;Koo, Doe-Gyoon;Lee, Jie-Tae;Cho, Hyun-Ju;Han, Young-A;Sohn, Sung-Ok;Ji, Byung-Chul
    • International Journal of Control, Automation, and Systems
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    • v.4 no.6
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    • pp.763-768
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    • 2006
  • The two-for-one(TFO) twister is precision machinery that twists fibers rapidly under constant tension. Since the quality of the twisted yarn is directly deteriorated by faults of the twister, such as the distortion of the spinning axis, bearing abrasion, and tension irregularity, it is important to detect faults of the TFO twister at an early stage. In this research, a new algorithm is proposed to detect faults of the TFO twister and their causes, by measuring the vibrations of the TFO twister and obtaining frequency components with a FFT algorithm. The TFO twister with faults showed increased vibrations and each fault generated vibrations at different frequencies. By analyzing changes of characteristics of vibrations, we can determine faulty twisters. The proposed fault detection algorithm can be implemented cheaply with a signal processor chip. It can be used to find when to repair a faulty TFO twister without much loss of yam on-line.

Realtime Digital Monitoring and Controller Development for Power Systems (전력시스템의 실시간 디지털 중앙감시 및 제어장치 개발)

  • Jong-Dug Cho;Sun-Hag Hong
    • Journal of the Korea Computer Industry Society
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    • v.2 no.12
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    • pp.1517-1522
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    • 2001
  • In this paper, We propose digital protective relay which monitors the status of distribution line and controls power apparatus with real time operation. Digital protective relay improves the performance of basic functions which are measurement, display and communication. The Int one we consider is that the protective device has the standard method for protecting the distribution systems which are circuit brakers, switch and emergency generators. These are Protected by analog type Protective relay and devices. The security requirements should be activated within a few seconds, and with real time operation. The second one is an efficient method for adapting the one chip micro-processor(PIC16F84) which is enable to digital control system. The proposed methods are implemented with experimental results and have an high fidelity characteristics in local experiment tests.

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