• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.59-62
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• 2002

BLDC motor is widely used in automation areas for its good maintenance and controllability. In this paper it is designed for a speed control servo system of sinusoidal typo BLDC motor that can be easily adapted to automation systems with lower cost. Also, control parameters & periods are made adjustable according to the sensors of the motor, electric and mechanical time constant, and PI and PD control are used. The processor for the proposed system is a low cost 16bit One-Chip microprocessor. By experimental results from application to the industrial sewing machine, one of the application of BLDC motor, it can be verified that under the given reference, the system is enough as a speed and position servo without overshoots.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.103-113
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• 2001

This paper described a design and implementation of a single-chip encoder/decoder using the LZSS algorithm and entropy coding in 0.6${\mu}{\textrm}{m}$ CMOS technology. Dictionary storage for the dictionary search processor(DISP) used a 2K$\times$8bit on-chip memory with 50MHz clock speed. It performs compression on byte-oriented input data at a data rate of one byte per clock cycle except when one out of every 33 cycles is used to update the string window of dictionary. In result, the average compression ratio is 46% by applied entropy coding of the LZSS codeword output. This is to improved on the compression performance of 7% much more then LZSS.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.758-761
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• 1991

Using one chip microcontroller 87Cl96 (On chip EPROM type) and EPLD (Erasable & Programable Logic Device), an implantable control system to drive pendulum type electromechanical total artificial heart was developed. This control system consists of 4 parts, main management system, motor driver with power regulator, state monitoring system and communication part. The main system has the functions for speed detection, PI(proportional and integration) control, PWM generation, communication and analog data processor. Two kinds of power system were used and separated by 8 photo coupler arrays to improve the system stability. The performances of each compartments were compared with our previous z80 microprocessor based control system and good correspondences was shown. Logic power consumption was reduced to a one third of our previous controller. Using mock circulation tests, the overall performances of control system are evaluated.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.863-867
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• 2003

This paper aims at the development of shoes measuring the performance of walking or running, which is equipped with electronic devices. In the in-sole of the shoes, a piezoelectric sensor is inserted for measuring the number of steps and the speed of walking. The measured signals are processed by the one-chip microprocessor and related electronic devices. Using the data, the momentum and calories of walking and running are calculated, and the results are transmitted to the displaying system composed of LCD by the RF telecommunication system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.709-711
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• 2016

An automatic control system to control a machinery system is managed by the PLC(Program Logic Control) and measured a machinery status from the sensor information to improve productivity in the industry field. This paper to propose a diagnostic monitoring system consists of a relay module, a one-chip processor module and a computer monitoring system. To improve productive capacity, the system is to check an auxiliary relay's trouble by a real-time monitoring.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.338-343
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• 2006

This paper describes about the design concept and the architecture of an economic VPN system which can perform fast crypto operations with cheap cost. The essence of the proposed system architecture is consisting of the system with two companion chips dedicated to VPN: one chip is a multi-purpose network processor for security machine and the other is a crypto acceleration chip which encrypt and decrypt network packets in a high speed. This study also addresses about some realizations that is required for fast prototyping such as the porting of an operating system, the establishment of compiler tool chain, the implementation of device drivers and the design of IPSec security engine. Especially, the second chip supports the most time consuming block cipher algorithms including 3DES, AES, and SEED and its performance was evaluated.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.7
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• pp.354-360
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• 2008

Power-related issues have become important considerations in current generation microprocessor design. One of these issues is that of elevated on-chip temperatures. This has an adverse effect on cooling cost and, if not addressed suitably, on chip reliability. In this paper we investigate the general trade-offs between temporal and spatial hot spot mitigation schemes and thermal time constants, workload variations and microprocessor power distributions. By leveraging spatial and temporal heat slacks, our schemes enable lowering of on-chip unit temperatures by changing the workload in a timely manner with Operating System (OS) and existing hardware support.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10a
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• pp.113-116
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• 1990

In this paper, An expert system for electric furnace with time delay is proposed. The expert system uses Fuzzy control theory. The conventional controller uses Auto-Tuning control theory. From experiment, we can obtain that the response of expert system is superior to the response of the conventional controller. In this experiment, the expert controller is implemented with the IBM PC. The 8751 One chip processor controling the electric furnace is used.

• The KIPS Transactions:PartA
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• v.13A no.5 s.102
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• pp.413-420
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• 2006

Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. We already addressed how to efficiently assign data to multi-memory banks in our previous work. This paper reports on our recent attempt to optimize run-time memory. The run-time environment for dual data memory banks (DBMBs) requires two run-time stacks to control activation records located in two memory banks corresponding to calling procedures. However, activation records of two memory banks for a procedure are able to have different size. As a consequence, dual run-time stacks can be unbalanced whenever a procedure is called. This unbalance between two memory banks causes that usage of one memory bank can exceed the extent of on-chip memory area although there is free area in the other memory bank. We attempt balancing dual run-time slacks to enhance efficiently utilization of on-chip memory in this paper. The experimental results have revealed that although our algorithm is relatively quite simple, it still can utilize run-time memories efficiently; thus enabling our compiler to run extremely fast, yet minimizing the usage of un-time memory in the target code.

• Journal of IKEEE
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• v.21 no.1
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• pp.92-95
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• 2017

In this paper, we proposed a way to improve function of small scale GP-GPU. Instead of using superscalar which increase scheduling-complexity, we suggested the application of simple core to maximize GP-GPU performance. Our studies also demonstrated that simplified Stream Processor is one of the way to achieve functional improvement in GP-GPU. In addition, we found that developing of optimal thread-assigning method in Warp Scheduler for specific application improves functional performance of GP-GPU. For examination of GP-GPU functional performance, we suggested the thread-assigning way which coordinated with Deep-Learning system; a part of Neural Network. As a result, we found that functional index in algorithm of Neural Network was increased to 90%, 98% compared with Intel CPU and ARM cortex-A15 4 core respectively.