• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 추계학술대회 논문집 학회본부
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• pp.308-310
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• 1996

Recently, as a result of the progress in power electronics and microelectronics, the inverter technology is quickly developing. Also, by using the fast microprocessor and small-sized switching devices, such as IPM, the Inverter becomes more compact and cheap. This paper proposes an inexpensive and small-sized vector controller for induction motors using 87C196MC and IPM. The proposed inverter contributes further space-saving, and high performance features to motor drives system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 A
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• pp.318-320
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• 1995

This paper describes the practical implementation of switched reluctance motor drive for a wide range of operation speeds. The angle controller is designed by one-chip microprocessor 8051 for various real time applications. Algorithm to control the speed of SRM and to maintain the speed under the changed load is proposed.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 1998년도 특별강연 및 추계학술발표 개요집
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• pp.160-163
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• 1998

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부A
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• pp.179-181
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• 1998

In this paper, one chip PWM pattern generator which eliminates time delay of computations and improves utilization factor of voltage is proposed. Both amplitude of sinusoidal signal and triangular signal are directly controlled. Thus, time delay of computations can be eliminated, and it is possible to track accurately instantaneous current for a sudden change of load with microprocessor 80C196KC. In addition, setting dead-time is also possible for wide range. From experimental work with inverter system for driving induction motor, the validity of proposed one chip PWM pattern generator is verified.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 연구회 합동 학술발표회 논문집
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• pp.5-8
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• 1998

The adaptation to vector control theory is so generalized that it is widely used for implementing the high-performance of AC machine. Nowadays, One-Chip microprocessors or DSP chips are being well-used to implement Vector Control algorithm. DSP Chip have less flexibility for memory decoding and I/O rather than One-Chip microprocessor so that is requires more additional circuit and high cost. And the past One-Chip micro processors have difficult of implementation the complex algorithm because of small memory capacity and low arithmetic performance. Therefore we implemented the vector control algorithm of PMSM(Permanent Magnetic Synchronous Motors) using 80296SA form intel , which have many features as 6M memory space, 500MHz clock frequency, including memory decoding circuit and general I/O, Special I/O(EPA, Interrupt controller, Timer/Count, PWM generator) which is proper controller for the complex algorithm or operation program requiring so much memory capacity, So in this paper we fully digitized the vector control of PMSM included SVPWM Voltage controller using the intel 80296SA

• 제어로봇시스템학회논문지
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• 제5권7호
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• pp.855-861
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• 1999

In this paper, we present new application for the auction method which has been based on one-chip microprocessors. We develop the portable wired terminal for market blocker. And, using that, the recommended price of products is able to push into and show the information of action status. Through our research, using EAS(Electronic Auction System), we can prevent supplier from blocker's rigging the market, because anyone who have a qualification for the action blocker is able to participate in action.

• 한국정보과학회논문지:시스템및이론
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• 제35권7호
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• pp.354-360
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• 2008

최신의 마이크로프로세서 설계에서는 전력 관련 문제들이 중요한 고려사항이 되었다. 온-칩(On-chip) 온도 상승은 이와 관련하여 중요한 요소로 부각되었다. 이를 적절하게 처리하지 않을 경우 냉각 비용과 칩 신뢰성에 부정적인 결과를 초래한다. 이 논문에서 우리는 시간적/공간적인 핫 스폿(Hot spot) 완화를 위한 설계들과 열 시간 상수, 작업부하 변동, 마이크로프로세서의 전력 분배 사이의 보편적인 상충관계(Trade off)들을 조사한다. 우리의 방안은 작업부하의 실행위치/순서를 변경하고 동시실행 스레드의 수를 조절하여 시스템의 공간 및 시간적인 열 틈새(Heat slack)에 영향을 줌으로써, 운영체계(OS)와 이미 시스템에 존재하는 하드웨어의 지원만으로 적절한 시간제한내에 작업부하를 조절함으로써 온-칩 온도를 낮출 수 있다.

• 수산해양기술연구
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• 제32권1호
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• pp.78-84
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• 1996

Recently, the fact that welding conditions are dangerous for men and the shapes of seams are complex enforced the welding system to be automatic. In order to obtain this target, are chip Microprocessor controlled welding system is devised in this study. The tracking of seam shape is achieved by applying a differential transformer and by using a program developed. This welding system mainly consists of a sensor, the differential transformer, a servo power amplifier, a control system, and DC motors. It is verified that the developed welding system is able to track three kinds of seam shapes.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1016-1021
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• 2003

The overall size of electronic product is becoming small according to development of technology. Accordingly it is difficult to inspect these small components by human eyes. So, an automation system for inspecting them has been used. The existing system put microprocessor or Programmable Logic Controller (PLC) use. The structure of microprocessor-based controller and PLC use basically composed of memory devices such as ROM, RAM and I/O ports. Accordingly, the system is not only becomes complicated and enlarged but also higher price. In this paper, we implement FPGA-based One-chip Programmable Timing Controller for Inspecting Small components to resolve above problems and design the high performance controller by using VHDL. With fast development, the FPGA of high capacity that can have memory and PLL have been introduced. By using the high-capacity FPGA, the peripherals of the existent controller, such as memory, I/O ports can be implemented in one FPGA. By doing this, because the complicated system can be simplified, the noise and power dissipation problems can be minimized and it can have the advantage in price. Since the proposed controller is organized to have internal register, counter, and software routines for generating timing signals, users do not have to problem the details about timing signals and need to only send some values about an inspection system through an RS232C port. By selecting theses values appropriate for a given inspection system, desired timing signals can be generated.