• Title/Summary/Keyword: One keystream Bit

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Finding New Algebraic Relations on Some Combiners with Memory And Its Applications (메모리를 가지는 Combiner 모델에 대한 새로운 대수적 방정식 구성 방법과 그 응용)

  • Kim, Jaeheon;Han, Jae-Woo;Moon, Dukjae
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.16 no.1
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    • pp.65-70
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    • 2006
  • It is hewn that we can apply algebraic attacks on combiners with memory such as summation generators. [1,8] To apply algebraic attacks on combiners with memory, we need to construct algebraic relations between the keystream bits and the initial bits of the LFSRs. Until now, all known methods produce algebraic relations involving several consecutive bits of keystream. [l.4.8] In this paper, we show that algebraic relations involving only one keystream bit can be constructed for summation generators. We also show that there is an algebraic relation involving only one keystream bit for ISG (9) proposed by Lee and Moon. Using this fact, we analyze the keystream generators which generate the keystreams by combining summation generators.

On a High-speed Implementation of LILI-II Stream Cipher (LILI-II 스트림 암호의 고속화 구현에 관한 연구)

  • 이훈재;문상재
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.8C
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    • pp.1210-1217
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    • 2004
  • LILI-II stream cipher is an upgraded version of the LILI-128, one of candidates in NESSIE. Since the algorithm is a clock-controlled, the speed of the keystream data is degraded structurally in a clock-synchronized hardware logic design. Accordingly, this paper proposes a 4-bit parallel LFSR, where each register bit includes four variable data routines for feedback or shifting within the LFSR. furthermore, the timing of the proposed design is simulated using a Max+plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and apply to the Lucent ASIC device (LV160C, 0.13${\mu}{\textrm}{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13${\mu}{\textrm}{m}$ semiconductor for the maximum path delay below 1.8㎱. Finally, we propose the m-parallel implementation of LILI-II, throughput with 4, 8 or 16 Gbps (m=8, 16 or 32).