• Journal of Mechanical Science and Technology
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• v.14 no.9
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• pp.997-1004
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• 2000

The experiments were conducted by using water and paraffin slurry to investigate the effect of a chip spacing in the multichip module on the cooling characteristics from an in-line $4{\times}3$ array of discrete heat sources which were flush mounted on the top wall of a channel. The experimental parameters were chip spacing in a multichip module, heat flux of simulated VLSI chip, mass fraction of paraffin slurry, and channel Reynolds number. The removable heat flux at the same chip surface temperature decreased as the chip spacing decreased at the first and fourth rows. The local heat transfer coefficients for the paraffin slurry were larger than those for water, and the chip spacing on the local heat transfer coefficients for paraffin slurry influenced less than that for water. The enhancement factor for paraffin slurry showed the largest value at a mass fraction of 5% regardless of the chip spacing, and the enhancement factors increased as the chip spacing decreased. This means that the paraffin slurry is more effective than water for cooling of the highly integrated multichip module.

• Proceedings of the KSME Conference
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• 2001.06d
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• pp.546-552
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• 2001

The heat transfer and flow measurements on a pedestal encountered in chip cooling. A uniform wall temperature boundary condition at the plate surface and on a pedestal was created using shroud method. Liquid crystal was used to measure the plate surface temperature. The jet Reynolds number (Re) ranges from 11,000 to 50,000, the dimensionless nozzle-to-surface distance (L/d) from 2 to 10, and the dimensionless pedestal diameter-to-height (H/D) from 0 to 1.0. The results show that the Nusselt number distributions at the near the pedestal exhibit secondary maxima at $r/d{\cong}1.0\;and\;1.5$. The formation of the secondary maxima is attributed to an create in the vortex by the pedestal.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.9
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• pp.1615-1620
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• 2010

A thin film thermoelectric cooler for COB direct assembly was proposed and the COB cooler structure was modeled by electrical equivalent circuit by using SPICE model of thermoelectric devices. The embedded cooler attached between the die chip and metal plate can offer the possibility of thin film active cooling for the COB direct assembly. We proposed a driving method of TEC by using pulse width modulation technique. The optimum power to the TEC is simulated by using a SPICE model of thermoelectric device and passive components representing thermal resistance and capacitance. The measured and simulated results offer the possibility of thin film active cooling for the COB direct assembly.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.21 no.8
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• pp.973-982
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• 1997

Effect of vortex generator on the heat transfer enhancement of electronic chips is investigated using naphthalene sublimation technique. Experiments are performed for a single chip and chip arrays, and shape of vortex generator, position of vortex generator, stream wise chip spacing and air velocity are varied. Local and average heat transfer coefficients are measured on the top surface of simulated electronic chips, and compared with those obtained without vortex generator. In case of a single chip, heat transfer augmentation is seen only on the upstream portion of chip surface, while heat transfer enhancement is found on the whole surface for chip arrays. Rectangular wing type vortex generator is found to be more effective than delta wing.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.10 no.3
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• pp.53-59
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• 2011

In this study, a two-phase closed loop cooling system is desinged and tested for a laptop computer using a FC-72. The cooling system is characterized by a parametric study which determines the effects of existence of a boiling enhancement microstructure, initial system pressure, volume fill ratio of coolant and inclination angle of condenser on the thermal performance of the closed loop. Experimental data show the optium condition when the volume ratio of working fluid is 70%, the pump flowing is 6ml/min, and the inclination angle of condenser is $0^{\circ}$. This research shows the maximum values which can dissipate 33W of chip power with a chip temperature maintained at $95^{\circ}C$.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.6
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• pp.774-782
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• 2004

This article presents a numerical and experimental investigation for the single-phase forced laminar convective heat transfer through arrays of micro-channels in micro heat exchangers to be used for cooling power-intensive semiconductor packages, especially the stacked multi-chip modules. In the numerical analysis, a parametric study was carried out for the parameters affecting the efficiency of heat transfer in the flow of coolants through parallel rectangular micro-channels. In the experimental study, the cooling performance of the micro heat exchanger was tested on prototypes of stacked multi-chip modules with difference channel dimensions. The simulation results and the experiment data were acceptably accordant within a wide range of design variations, suggesting the numerical procedure as a useful method for designing the cooling mechanism in stacked multi-chip packages and similar electronic applications.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.17 no.3
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• pp.14-19
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• 2008

In the semiconductor IC(Integrated Circuit) package, the top surface of silicon chip is directly attached to the area of the leadframe with a double-sided adhesive layer, in which the base layer have the upper adhesive layer and the lower adhesive layer. The IC package structure has been known to encounter a thermo-mechanical failure mode such as delamination. This failure mode is due to the residual stress on the adhesive surface of silicon chip and leadframe in the curing-cooling process. The induced thermal stress in the curing process has an influence on the cooling residual stress on the silicon chip and leadframe. In this paper, for the minimization of the chip surface damage, the adhesive topologies on the silicon chip are studied through the finite element analysis(FEA).

• Journal of the Korean Society for Precision Engineering
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• v.24 no.12
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• pp.95-103
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• 2007

This paper presents a liquid cooling concept for heat rejection of high power electronic devices existing in notebook computers etc. The design, fabrication, and performance of the planar ECF pump and farced-liquid cooling system are summarized. The electro-conjugate fluid (ECF) is a kind of dielectric and functional fluids, which generates jet flows (ECF-jets) by applying static electric field through a pair of rod-like electrodes. The ECF-jet directly acts on the working fluid, so the proposed planar ECF pump needs no moving part, produces no vibration and noise. The planar ECF pump, consists of a pump housing and electrode substrate, achieves maximum flow rate and output pressure of $5.5\;cm^3/s$ and 7.2 kPa, respectively, at an applied voltage of 2.0 kV. The farced-liquid cooling system, constructed with the planar ECF pump, liquid-cooled heat sink and thermal test chip, removes input power up to 80 W keeping the chip surface temperature below $70\;^{\circ}C$. The experimental results demonstrate that the feasibility of forced-liquid cooling system using ECF is confirmed as an advanced cooling solution on the next-generation high power electronic devices.

• Journal of the Korean Physical Society
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• v.73 no.9
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• pp.1346-1350
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• 2018

An electrode-evaporation technology on both the top and bottom sides of the bare vertical-type single chip separated from the traditional substrate by cooling, was developed for III-nitride vertical-type single chip LEDs with thick GaN epilayer. The post-process of the cooling step was followed by sorting the bare vertical-type single chip LEDs into the holes in a pocket-type shadow mask for deposition of the electrodes at the top and bottom sides of bare vertical-type single chip LEDs without the traditional substrate for electrode evaporation technology for vertical-type single chip LEDs. The variation in size of the hole between the designed shadow mask and the deposited electrodes owing to the use of the designed pocket-type shadow mask is investigated. Furthermore, the electrical and the optical properties of bare vertical-type single chip LEDs deposited with two different shapes of n-type electrodes using the pocket-type shadow mask are investigated to explore the possibility of the e-beam evaporation method.

• Proceedings of the SAREK Conference
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• 2007.11a
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• pp.640-645
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• 2007

An experimental apparatus to show the hot spot cooling of an IC chip using a thermoelectric cooler is developed. The spot heating in very small area is achieved by the applying CO$_2$ laser source and temperatures are measured using miniature thermocouples. The active effects of thermoelectric cooler on the hot spot cooling system such as rapid heat spreading in the chip and lowering the peak temperature around the hot spot region are investigated. The experimental results are simulated numerically using the TAS program, which the performance characteristics such as Seebeck coefficient, electrical resistance and thermal conductivity of the thermoelectric cooler are searched by trial and error. Good agreements are obtained between numerical and experimental results if the appropriate performance data of the thermoelectric cooler are given.