• 대한전자공학회논문지SD
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• 제37권6호
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• pp.34-42
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• 2000

우수한 성능을 가지며 소형${\cdot}$경량인 무선통신기기를 구현하기 위해서는 GHz 대의 고주파수에서 동작하는 소형 RF chip 인덕터의 개발은 중요한 연구분야가 되어왔다. 또한 최근 많이 사용되는 자성 ferrite core 재료는 300MHz 이상의 주파수영역에서 자화율이 급속하게 감소하여 고성능 RF chip 인덕터 개발에 큰 장애가 되고 있다. 따라서 본 논문에서는 비정질 $Al_2O_3$ 코아 재료를 응용한 단순 solenoid 형태의 소형${\cdot}$고성능 RF chip 인덕터를 연구하였다. Cu를 코일 (직경=40${\mu}m$)로 사용하였고 인덕터 크기는 $2.1mm{\times}1.5mm{\times}1.0mm$였다. 외부 전류원은 코일의 양단을 코아 가장자리에 적층된 Au 막에 본딩시킨 후 인가되었다. 코아의 성분은 EDX를 사용하여 분석하였다 개발된 인덕터의 인덕턴스 (L), quality factor (Q), 인피던스(Z)등의 주파수 특성은 RF impedance/Material Analyzer (HP16193A test fixture가 장착된 HP4291B)로 측정되었다. 인덕터들의 인덕턴스 값은 22 nH ~ 150 nH 범위를 가지며, 이들의 자기공진주파수 (SRF)는 1~3.5GHz 영역을 나타낸다. 또한 자기공진주파수가 증가함에 따라 인덕턴스 값이 감소하는 경향을 보이고 있다. 임피던스는 공진주파수에서 최대 값을 가지며 Q-factor의 값은 500 MHz ~ 1.5 GHz 주파수 범위에서 최대 70~97까지 얻어졌다.

• Journal of information and communication convergence engineering
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• 제13권3호
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• pp.172-179
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• 2015

Face-to-face (F2F) bonding in three-dimensional integrated circuits (3D ICs), compared with other bonding styles, is closer to commercialization because of its benefits in terms of density, yield, and cost. However, despite the benefits that F2F bonding expect to provide, it's physical nature has not been studied thoroughly. In this study, we, for the first time, extract cross-die (inter-die) parasitic elements from F2F bonds on the full-chip scale and compare them with the intra-die elements. This allows us to demonstrate the significant impact of field sharing across dies in F2F bonding on full-chip noise and critical path delay values. The baseline method used is the die-by-die method, where the parasitic elements of individual dies are extracted separately and the cross-die parasitic elements are ignored. Compared with this inaccurate method, which was the only method available until now, our first-of-its-kind holistic method corrects the delay error by 25.48% and the noise error by 175%.

• 전기전자학회논문지
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• 제1권1호
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• pp.1-10
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• 1997

It is well-known that rectangular bulk-Si sensors prepared by etch or epi etch-stop micromachining technology are already in practical use today, but the conventional bulk-Si sensor shows some drawbacks such as large chip size and limited applications as silicon sensor device is to be miniaturized. We consider a circular-shape SOI(Silicon-On-Insulator) micro-cavity technology to facilitate multiple sensors on very small chip, to make device easier to package than conventional sensor like pressure sensor and to provide very high over-pressure capability. This paper demonstrates the cross-functional results for stress analyses(targeting $5{\mu}m$ deflection and 100MPa stress as maximum at various applicable pressure ranges), for finding permissible diaphragm dimension by output sensitivity, and piezoresistive sensor theory from two-type SOI structures where the double SOI structure shows the most feasible deflection and small stress at various ambient pressures. Those results can be compared with the ones of circular-shape bulk-Si based sensor$^{[17]}. The SOI micro-cavity formed the sensors is promising to integrate with calibration, gain stage and controller unit plus high current/high voltage CMOS drivers onto monolithic chip.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.651-654
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• 2005

In this paper, we designed ECC(Elliptic Curve Cryptographic) Processor with Bus-splitting mothod for embedded SoC. ECC SIP is designed by VHDL RTL modeling, and implemented reusably through the procedure of logic synthesis, simulation and FPGA verification. To communicate with ARM9 core and SIP, we designed SIP bus functional model according to AMBA AHB specification. The design of ECC Processor for platform-based SoC is implemented using the design kit which is composed of many devices such as ARM9 RISC core, memory, UART, interrupt controller, FPGA and so on. We performed software design on the ARM9 core for SIP and peripherals control, memory address mapping and so on.

• Journal of information and communication convergence engineering
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• 제9권6호
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• pp.729-732
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• 2011

Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• 진공이야기
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• 제4권3호
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• pp.16-20
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• 2017

Graphene has emerged as a promising material for optoelectronic applications including as ultrafast and broadband photodetector, optical modulator, and nonlinear photonic devices. Graphene based devices have shown the feasibility of ultrafast signal processing for required for photonic integrated circuits. However, on-chip monolithic nanoscale light source has remained challenges. Graphene's high current density, thermal stability, low heat capacity and non-equilibrium of electron and lattice temperature properties suggest that graphene as promising thermal light source. Early efforts showed infrared thermal radiation from substrate supported graphene device, with temperature limited due to significant cooling to substrate. The recent demonstration of bright visible light emission from suspended graphene achieve temperature up to ~3000 K and increase efficiency by reducing the heat dissipation and electron scattering. The world's thinnest graphene light source provides a promising path for on-chip light source for optical communication and next-generation display module.

• 한국세라믹학회지
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• 제36권6호
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• pp.583-589
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• 1999

In the fabrication of ceramic chip couples for high frequency application such as the mobile communication equipment the formation of electrode lines and Ag diffusion were investigated with heat treatment conditions for removing organic binders. The deformation and densification of the electrode line greatly depended on the binder burnout process due to the overlapped temperature zone near 400$^{\circ}C$ of the binder dissociation and the solid phase sintering of the silver electrode. Ag ions were diffused into the glass ceramic substrate. The Ag diffusion was led by the glassy phase containing Pb ions rather than by the crystalline phase containing Ca ions. The fact suggests that the Ag diffusion could be controlled by managing the composition of the glass ceramic substrate.

• Transactions on Electrical and Electronic Materials
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• 제13권3호
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• pp.129-135
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• 2012

A number of surface mount technology (SMT) process variables including land design are considered for minimizing tombstone defect in flexible printed circuit assembly in high volume manufacturing. As SMT chip components have been reduced over the past years with their weights in milligrams, the torque that once helped self-centering of chips, gears to tombstone defects. In this paper, we have investigated the correlation of the assembly process variables with respect to the tombstone defect by employing statistically designed experiment. After the statistical analysis is performed, we have setup hypotheses for the root causes of tombstone defect and derived main effects and interactions of the process parameters affecting the hypothesis. Based on the designed experiments, statistical analysis was performed to investigate significant process variable for the purpose of process control in flexible printed circuit manufacturing area. Finally, we provide beneficial suggestions for find-pitch PCB design, screen printing process, chip-mounting process, and reflow process to minimize the tombstone defects.

• Journal of information and communication convergence engineering
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• 제18권4호
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• pp.245-253
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• 2020

The human body and nervous system transmit information through electric charges. After the electric charge transmits information to the brain, we can feel pain, numbness, comfort, and other feelings. Electric therapy is currently used widely in clinical practice because the field of examination is more representative of electrocardiogram, and in the field of treatment is more representative of electrotherapy. In this study, we design a system for neurophysiological therapy and conduct parameter calculation and model selection for the components of the system. The system is based on a discontinuous conduction mode (DCM) boost circuit, and controlled and regulated by a single-chip microcomputer. The system does not only have a low cost but also fully considers the safety of use, convenience of the human-computer interface, adjustment sensitivity, and waveform diversity in the design. In future, it will have strong implications in the field of electrotherapy.

• 한국정보통신학회논문지
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• 제16권2호
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• pp.313-318
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• 2012

본 논문에서는 $30{\mu}m$ 이하의 초 미세 피치를 가진 칩 온 필름(chip-on-film, COF)에서 자주 발생하는 결함을 자동으로 검출할 수 있는 시스템을 제안한다. 개발된 시스템은 초 미세 패턴의 개방 및 단락 결함 뿐만아니라 소프트 개방 및 소프트 단락을 신속히 검출할 수 있는 회로 및 기술이 적용되어 있다. 결함 검출의 기본 원리는 결함 전의 패턴 저항값과 결함 후의 패턴 저항값 차에 의해 발생하는 미세 차동 전압을 읽어서 결함 유무를 판단한다. 또한 미세전압 차를 증폭시켜 결함 유무를 쉽게 판단할 수 있도록 고주파 공진기를 이용한다. 제안된 시스템은 초미세 패턴 COF 검사 과정에서 발생하는 다양한 결함을 신속하고 정확히 검출할 수 있으므로 기존의 COF 검사 시스템의 대안이 될 것으로 기대한다.