• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.4
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• pp.59-64
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• 2009

In this paper, we represent characteristics and equivalent circuit of donut type resonator of defected ground structure (DGS), and can control resonant frequency with chip capacitor. In General, DGS operates like with parallel LC resonator. We found out variation of resonance frequency when capacitor is placed on slot of DGS. If the chip capacitor replace with varactor diode, the resonance frequencies can be controlled by voltage. This tualable resonator can apply to voltage controlled oscillator and tunable bandpass filter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.202-211
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• 2014

The bulk current injection (BCI) and direct power injection (DPI) method have been established as the standards for the electromagnetic susceptibility (EMS) test. Because the BCI test uses a probe to inject magnetically coupled electromagnetic (EM) noise, there is a significant difference between the power supplied by the radio frequency (RF) generator and that transferred to the integrated circuit (IC). Thus, the immunity estimated by the forward power cannot show the susceptibility of the IC itself. This paper derives the real injected power at the failure point of the IC using the power transfer efficiency of the BCI method. We propose and mathematically derive the power transfer efficiency based on equivalent circuit models representing the BCI test setup. The BCI test is performed on I/O buffers with and without decoupling capacitors, and their immunities are evaluated based on the traditional forward power and the real injected power proposed in this work. The real injected power shows the actual noise power level that the IC can tolerate. Using the real injected power as an indicator for the EMS test, we show that the on-chip decoupling capacitor enhances the EM noise immunity.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.07a
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• pp.326-326
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• 2004

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.869-872
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• 2005

In this paper we present a switch wrapper for an AMBA AXI, which is an efficient on-chip-network interface compared to bus-based interfaces in a multiprocessor SoC. The AXI uses an idea of NoC to provide the increasing demands on communication bandwidth within a single chip. A switch wrapper for AXI is located between a interconnection network and two IPs connecting them together. It carries out a mode of routing to interconnection network and executes protocol conversions to provide compatibility in IP reuse. A switch wrapper consists of a direct router, AHB-AXI converters, interface modules and a controller modules. We propose the design of a all-in-one type switch wrapper.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1089-1095
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• 2005

This paper presents a new low-cost Built-In Self-Test (BIST) circuit for 50Hz low noise amplifier (LNA). The BIST circuit is designed for system-on-chip (SoC) transceiver environment. The proposed BIST circuit measures the LNA specifications such as input impedance, voltage gaih, noise figure, and input return loss all in a single SoC environment.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1776-1778
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• 2000

The demands placed on portable wireless communication equipment include low cost, low supply voltage, low power, dissipation, low noise, high frequency of operation, and low distortion. These design requirements cannot be met satisfactorily in many cases without the use of RF inductors. However, implementing the inductor on-chip has been regarded as an impractical task because of excessive substrate capacitance and substantial resistive losses due to metallization and the conductive silicon substrate. Hence, there is a great incentive to design, optimize, and model spiral inductors on Si substrate. So, we analyzed a chip inductors using electromagnetic analysis and established a set of design rules for rectangular spiral inductors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.86-94
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• 2007

The NoC (network-on-chip) approach is a promising solution to the increasing complexity of on-chip communication problems because of its high scalability. But, NoC applications generally consume a lot of power, because they require a large design space to accommodate many parallel IPs and network communication channels. It is not easy to analyze the power consumption of NoC applications with conventional simulation methods using simple power models. In addition, there are also many limitations in using sophisticated simulation models because they require long execution time and large efforts. In this paper, we apply a cycle-accurate energy measurement technique and tool to the FPGA prototypes, which are generally used to verify the correctness of SoC designs, as a practical indication of the power consumption of real NoC applications. An NoC-based JPEG encoder implementation is used as a case study to demonstrate the effectiveness of our approach.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.885-888
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• 2015

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connect (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 40K at an operating frequency of 250MHz using the $0.13{\mu}m$ TSMC process.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1990.06a
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• pp.539-542
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• 1990

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.25-32
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• 2009

Recently, research for Network-on-chip(NoC) is progressing. However, due to the increase of system complexity and demand on high performance, conventional copper-based electrical interconnect would be faced with the design limitation of performance, power, and bandwidth. As an alternative to these problems, combined use of Electrical Interconnects(EIs) and Optical Interconnects(OIs) has been introduced. In this paper we propose efficient routing optimization strategy and hybrid switch architecture, which use OIs for critical path and EIs for non-critical path. The proposed method shows up to 25% performance improvement and 38% power reduction.