• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.19-23
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• 2002

This paper presents a micro fluxgate magnetic sensor in printed circuit board (PCB). In order to observe the effect of the closed magnetic path, the magnetic cores of rectangular-ring and two bars were each fabricated. Each fluxgate sensor consists of five PCB stack layers including one layer magnetic core and four layers of excitation and pick-up coils. The center layer as a magnetic core is made of a Co-based amorphous magnetic ribbon with extremely high DC permeability of ~100,000. Four outer layers as an excitation and pick-up coils have a planar solenoid and are made of copper foil. In case of the fluxgate sensor having the rectangular-ring shaped core, excellent linear response over the range of -100 $\mu$T to ＋ 100 $\mu$T is obtained with 540 V/Tsensitivity at excitation square wave of 3 $V_{p-p}$ and 360 KHz. The chip size of the fabricated sensing element is $7.3 \times 5.7\textrm{mm}^2$. The very low power consumption of ~8 mW was measured. This magnetic sensor is very useful for various applications such as: portable navigation systems, telematics, VR game and so on.n.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.4
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• pp.61-68
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• 2023

In this study, Sn-3.5Ag-15.0Fe composite solder was manufactured and applied to TLP bonding to change the entire joint into a Sn-Fe IMC(intermetallic compound), thereby applying it as a high-temperature solder. The FeSn₂ IMC formed during the bonding process has a high melting point of 513℃, so it can be stably applied to power modules for power semiconductors where the temperature rises up to 280℃ during use. As a result of applying ENIG surface treatment to both the chip and substrate, a multi-layer IMC structure of Ni₃Sn₄/FeSn₂/Ni₃Sn₄ was formed at the joint. During the shear test, the fracture path showed that cracks developed at the Ni₃Sn₄/FeSn₂ interface and then propagated into FeSn₂. After 2hours of the TLP joining process, a shear strength of over 30 MPa was obtained, and in particular, there was no decrease in strength at all even in a shear test at 200℃. The results of this study can be expected to lead to materials and processes that can be applied to power modules for electric vehicles, which are being actively researched recently.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.189-195
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• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.37-43
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• 2010

As the speed of A/V streaming, the transmission-speed requirement of serial link is continuously increasing. Consequently, commercial standards, which are released previously, are increasing transmission speed in their newly-updated versions. The flexibility between previous and updated versions is very important requirement, therefore, the transceiver which can operates at more than one data rate is important market demand. This paper demonstrates 4-channel 3.2/ 6.4 Gbps transmitter, which is capable of selecting 1, 1.5, 2, and 3 times of pre-emphasis and 200, 300, 400, and 600 mVdiff,p2p of output swing. The prototype chip was fabricated using $0.13{\mu}m$ CMOS process. Its performances are verified on PCB using COB packaging.

• Korean Journal of Optics and Photonics
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• v.8 no.6
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• pp.510-515
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• 1997

Packaging takes an extremely important element of optical module cost due primarily to the added complication of alignment between semiconductor devices and optical fiber, and many efforts have been devoted on reducing the cost by eliminating the complicated optical alignment procedures in passive manner. In this study, we fabricated silicon optical benches on which the optical alignments are accomplished passively. To improve the positioning accuracy of a flip-chip bonded LD, we adopted fiducial marks and solder dams which are self-aligned with V-groove etch patterns, and a stand-off to control the height and to improve the heat dissipation of LD. Optical sub-assemblies exhibited an average efficiency of -11.75$\pm$1.75 dB(1$\sigma$) from the LD-to-single mode fiber coupling and an average sensitivity of -35.0$\pm$1.5 dBm from the fiber and photodetector coupling.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.2
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• pp.245-253
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• 2010

The reliability problems of flip chip packages subjected to temperature change during the packaging process mainly occur due to mismatches in the coefficients of thermal expansion as well as features with time-dependent material properties. Resin molding compounds like glass fiber reinforced epoxy composites used as the dielectric layer in printed circuit boards (PCB) strongly exhibit viscoelastic behavior, which causes their Young's moduli to not only be temperature-dependent but also time-dependent. In this study, the stress relaxation and creep tests were used to characterize the viscoelastic properties of the glass fiber reinforced epoxy composite. Using the viscoelastic properties, finite element analysis (FEA) was employed to simulate thermal loading in the pre-baking process and predict thermal warpage. Furthermore, the effect of viscoelastic features for the major polymeric material on the dielectric layer in the PCB (the glass fiber reinforced epoxy composite) was investigated using FEA.

• Asia-Pacific Journal of Business Venturing and Entrepreneurship
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• v.7 no.3
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• pp.17-25
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• 2012

Wire bonding process in making semiconductor needs the most precise control and Critical To Quality(CTQ). Thus, it is regarded to be the most essential step in packaging process. In this process, pure gold wire is used to connect the chip and PCB(substrate or lead frame). However, the price of gold has been skyrocketing continuously for a long period of time and is expected to further increase in the near future. This phenomenon situates us in an unfavorable condition amidst the competitive environment. To avoid this situation, many semiconductor material making companies developed new types of wires: Au.Ag wire is one material followed by many others. This study is aimed to optimize the parameter in wire bonding with the use of 6sigma and QFD(Quality Function Deployment). 6sigma process is a good means to not only solve the problem, but to increase productivity. In order to find the key factor, we focused on VOB(Voice of Business) and VOC(Voice of Customer). The main factors from VOB, VOC are called CTQ. However, there were times when these main factors were far from offering us the correct answer, thus making the situation more difficult to handle. This study shows that QFD aids in deciding which of the accurate factors to undertake. Normally QFD is used in designing and developing products. 6sigma process is held more effective when it used with QFD.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.11a
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• pp.123-123
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• 2012

최근 연구되고 있는 TSV(Through Silicon Via) 기술은 Si 웨이퍼 상에 직접 전기적 연결 통로인 관통홀을 형성하는 방법으로 칩간 연결거리를 최소화 할 수 있으며, 부피의 감소, 연결부 단축에 따른 빠른 신호 전달을 가능하게 한다. 이러한 TSV 기술은 최근의 초경량화와 고집적화로 대표되는 전자제품의 요구를 만족시킬 수 있는 차세대 실장법으로 기대를 모으고 있다. 한편, 납땜 재료의 주 원료인 주석은 주로 반도체 소자의 제조, 반도체 칩과 기판의 접합 및 플립 칩 (Flip Chip) 제조시의 범프 형성 등 반도체용 배선재료에 널리 사용되고 있다. 최근에는 납의 유해성 때문에 대부분의 전자제품은 무연솔더를 이용하여 제조되고 있지만, 주석을 이용한 반도체 소자가 고밀도화, 고 용량화 및 미세피치(Fine Pitch)화 되고 있기 때문에, 반도체 칩의 근방에 배치된 주석으로부터 많은 알파 방사선이 방출되어 메모리 셀의 정보를 유실시키는 소프트 에러 (Soft Error)가 발생되는 위험이 많아지고 있다. 이로 인해, 반도체 소자 및 납땜 재료의 주 원료인 주석의 고순도화가 요구되고 있으며, 특히 알파 방사선의 방출이 낮은 로우알파솔더 (Low Alpha Solder)가 요구되고 있다. 이에 따라 본 연구는 4인치 실리콘 웨이퍼상에 직경 $60{\mu}m$, 깊이 $120{\mu}m$의 비아홀을 형성하고, 비아 홀 내에 기능 박막증착 및 전해도금을 이용하여 전도성 물질인 Cu를 충전한 후 직경 $80{\mu}m$의 로우알파 Sn-1.0Ag-0.5Cu 솔더를 접합 한 후, 접합부 신뢰성 평가를 수행을 위해 고속 전단시험을 실시하였다. 비아 홀 내 미세구조와 범프의 형상 및 전단시험 후 파괴모드의 분석은 FE-SEM (Field Emission Scanning Electron Microscope)을 이용하여 관찰하였다. 연구 결과 비아의 입구 막힘이나 보이드(Void)와 같은 결함 없이 Cu를 충전하였으며, 고속전단의 경우는 전단 속도가 증가할수록 취성파괴가 증가하는 경향을 보였다. 본 연구를 통하여 전해도금을 이용한 비아 홀 내 Cu의 고속 충전 및 로우알파 솔더 볼의 범프 형성이 가능하였으며, 이로 인한 전자제품의 소프트에러의 감소가 기대된다.