• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.2
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• pp.401-407
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• 2014

There are increasing interests in COB (Chip On Board) that densely arranged many LED chips on one board in order to solve the heat issue. There are many problems being on the rise: the lifespan decreases as the temperature of LED devices increases; Red Shift phenomenon, in which wave length of spectral line moves from original wave length to long wave length, occurs; and optical power decreases as $T_j$ increases. In order to resolve such problems, this study selected the optimum thickness and length of Fin, planned the second Heat sink that is optimum for COB LED with 15W, and analyzed thermal mode by Solid Works Flow Simulation through 15W COB packaging with the planned Heat sink. 15W COB down-light Heat sink that is produced based on this analysis was utilized to analyze thermal mode through contact thermometer and electrical properties through Kelthley 2430.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1978.1_1979.1
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• 2009

In this paper, we have proposed and demonstrated a tonometry sensor array for measuring arterial pulse pressure. A sensor module consists of 7 piezoresistive pressure sensor array. Wire-bonded connection was provided between silicon chip and lead frame. PDMS(poly-dimethylsiloxane) was coated on the sensor array to protect fragile sensor while faithfully transmitting the pressure of radial artery to the sensor. Tonometric pulse pressure can be measured by this packaged sensor array that provides the pressure value versus the output voltage.

• The Korean Journal of Ceramics
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• v.1 no.2
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• pp.96-100
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• 1995

Recently, alumina/glass composites have been applied as a substrate material for hybrid IC and LSI multi-chip packaging. In this study, the characterization of sodium borosilicate glasses containing NaF and $AlF_3$ and the preparation of the resulted glass/alumina composites have been examined and the effect of the addition of fluorides on the thermal. and dielectric properties of the sintered composites have been studied. The sintering temperature of specimens was lowered by about 100-$150^{\circ}C$ by the addition of fluorine compared with the specimens without fluorine. The specimens containing fluorine showed slightly lower dielectric constants than those of the specimens without fluorine.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.05a
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• pp.220-223
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• 1996

Mechanical properties of Plasma-Enhanced Chemical Vapor Deposited (PECVD) silicon nitride thin film was studied to determine the feasibility of the film as a passivation layer over the aluminum bonding areas of integrated circuit chips. Ultimate strain of the films in thicknesses of about 5 k${\AA}$ was measured using four-point bending method. The ultimate strain of these films was constant at about 0.2% regardless of residual stress. Intrinsic and residual stresses of these films were measured and compared with thermal shock and cycling test results. Comparison of the results showed that more tensile films were more susceptible to crack- induced failure.

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.146-149
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• 2007

1) 자체 제작한 NCP인 A, B, C 3종은 상용화 제품에 비해 도포성에 관련한 특성은 우수한 것으로 나타났으나 Tg 등의 열특성은 개선이 필요한 것으로 판단된다. 2) 접합강도의 경우 4종의 큰 차이가 없었으나 필러가 비교적 적은 조성인 B 조성의 경우 가장 큰 접합강도를 나타냈다. 3) NCP A, B, C 3종에 대한 접속저항 측정 결과 필러가 가장 많은 C의 경우가 가장 높은 저항 값을 보였으며 이는 가속 고온 고습 시험에 대한 결과에서도 급격한 접속률 감소를 통해 확인할 수 있다. 4) 시간에 따른 접속저항의 급격한 증가는 NCP 성분 중 친수성을 가진 물질이 있는 것이 원인이라 판단되며 이에 대한 개선을 통해 고습에 대한 신뢰성을 향상시킬 수 있을 것으로 보인다.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2006.09b
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• pp.1207-1208
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• 2006

We developed the copper core ball electroplated with Sn-Ag-Cu of the eutectic composition which used mostly as Pb free solder ball with high reliability. In order to search for the practicality of this developed copper core ball, the evaluation was executed by measuring the initial joint strength of the sample mounted on the substrate and reflowed and by measuring the joint strength of the sample after the high temperature leaving test and the constant temperature and the humidity leaving test. This evaluation was compered with those of the usual other copper core balls electroplated with (Sn,Sn-Ag,Sn-Cu,Sn-Bi) and the Sn-Ag-Cu solder ball.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2006.09a
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• pp.377-378
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• 2006

Thermal management technology is a critical element in all new chip generations, caused by a power multiplication combined with a size reduction. A heat sink, mounted on a base plate, requires the use of special materials possessing both high thermal conductivity (TC) and a coefficient of thermal expansion (CTE) that matches semiconductor materials as well as certain packaging ceramics. In this study, nano tungsten coated copper powder has been developed with a wide range of compositions, 90W-10Cu to 10W-90Cu. Powder technologies were used to make samples to evaluate density, TC, and CTE. Measured TC lies among theoretical values predicted by several existing models.

• Journal of the Semiconductor & Display Technology
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• v.17 no.1
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• pp.62-65
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• 2018

In the era of the 4th Industrial Revolution, IoT products of various and specialized fields are being developed and produced. Especially, the generation of the artificial intelligence, robotic technology Multilayer substrates and packaging technologies in the notebook, mobile device, display and semiconductor component industries are demanding the need for flexible materials along with miniaturization and thinning. To do this, this work use FCCL (Flexible Copper Clad Laminate), which is a flexible printed circuit board (PCB), to implement FPCB (Flexible PCB), COF (Chip on Film) Use is known to be essential. In this paper, I propose a transfer device which prevents the occurrence of scratches by analyzing the mechanism of wrinkle and scratch mechanism during the transfer process of thin film material in which the thickness increases while continuously moving in air or solution.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.124-130
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• 2023

Recently, fan out wafer level packaging, which enables high integration, miniaturization, and low cost, is being rapidly applied in the semiconductor industry. In particular, FOWLP is attracting attention in the mobile and Internet of Things fields, and is recognized as a core technology that will lead to technological advancements such as 5G, self-driving cars, and artificial intelligence in the future. However, as chip density and package size within the package increase, FOWLP warpage is emerging as a major problem. These problems have a direct impact on the reliability and electrical performance of semiconductor products, and in particular, cause defects such as vacuum leakage in the manufacturing process or lack of focus in the photolithography process, so technical demands for solving them are increasing. In this paper, warpage simulation according to the thickness of FOWLP material was performed using finite element analysis. The thickness range was based on the history of similar packages, and as a factor causing warpage, the curing temperature of the materials undergoing the curing process was applied and the difference in deformation due to the difference in thermal expansion coefficient between materials was used. At this time, the stacking order was reflected to reproduce warpage behavior similar to reality. After performing finite element analysis, the influence of each variable on causing warpage was defined, and based on this, it was confirmed that warpage was controlled as intended through design modifications.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.61-67
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• 2020

In this paper, we calculated the warpage of bare substrates and chip attached substrates by using FEM (Finite Element Method), and compared and analyzed the effect of the chips' attachment on warpage. Also, the effects of layer thickness of substrates for reducing warpage were analyzed and the conditions of layer thickness were analyzed by signal-to-noise ratio of Taguchi method. According to the analysis results, the direction of warpage pattern in substrates can change when chips are attached. Also, the warpage decreases as the difference in the CTE (coefficient of thermal expansion) between the top and bottom of the package decreases and the stiffness of the package increases after chips are loaded. In addition, according to the impact analysis of design parameters on substrates where chips are not attached, in order to reduce warpage, the inner layers of the circuit layer Cu1 and Cu4 has be controlled first, and then concentrated on the thickness of the solder resist on the bottom side and the thickness of the prepreg layer between Cu1 and Cu2.