• Journal of the Institute of Convergence Signal Processing
• /
• v.15 no.2
• /
• pp.70-75
• /
• 2014

Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.

• Journal of KIISE:Computer Systems and Theory
• /
• v.33 no.9
• /
• pp.699-708
• /
• 2006

Bus splitting technique reduces bus energy by placing modules with frequent communications closely and using necessary bus segments in communications. But, previous bus splitting techniques can not be used in MPSoC platform, because it uses cache coherency protocol and all processors should be able to see the bus transactions. In this paper, we propose a bus splitting technique for MPSoC platform to reduce bus energy. The proposed technique divides a bus into several bus segments, some for private memory and others for shared memory. So, it minimizes the bus energy consumed in private memory accesses without producing cache coherency problem. We also propose a task allocation technique considering cache coherency protocol. It allocates tasks into processors according to the numbers of bus transactions and cache coherence protocol, and reduces the bus energy consumption during shared memory references. The experimental results from simulations say the bus splitting technique reduces maximal 83% of the bus energy consumption by private memory accesses. Also they show the task allocation technique reduces maximal 30% of bus energy consumed in shared memory references. We can expect the bus splitting technique and the task allocation technique can be used in multiprocessor platforms to reduce bus energy without interference with cache coherency protocol.

• Journal of Plant Biotechnology
• /
• v.44 no.3
• /
• pp.264-270
• /
• 2017

Brassinosteroid (BR), a plant steroid hormone, plays a critical role in the growth and developmental processes through its canonical signaling and crosstalk with various internal and external signaling pathways. Recent studies have revealed the essential interplay mechanisms between BR and ABA during seed germination and early seedling establishment. However, molecular mechanisms for this important signaling crosstalk are largely unknown. To understand the crosstalk between BR-mediated signaling pathways and ABA functions during early seedling development, we carried out a comparative genome-wide transcriptome analysis with an Agilent Arabidopsis $4{\times}44K$ oligo chip. We selected and compared the expression patterns of ABA response genes in ABA-insensitive bes1-D mutant with wild type seedlings on which ABA was exogenously applied. As a result, we identified 2,353 significant differentially expressed genes (DEGs) in ABA-treated bes1-D and wild type seedlings. GO enrichment analysis revealed that ABA signaling, response, and metabolism were critically down-regulated by BR-activated signaling pathways. In addition, the genome-wide transcriptome analysis data revealed that BR-regulated signaling pathways were tightly connected to diverse signal cues including abiotic/biotic stress, auxin, ROS etc. In this study, we newly identified the molecular mechanisms of BR-mediated repression of ABA signaling outputs. Also, our data suggest that interplay among diverse signaling pathways is critical for the adaptive response of the plant to various environmental factors.

• The Korean Journal of Food And Nutrition
• /
• v.29 no.5
• /
• pp.670-676
• /
• 2016

In this study, we analyzed the utensils, covers and mats that were used for making meju, the shape of meju, and the heating method used for making meju from the 225 ways of preparing jang mentioned in the 32 volumes of the ancient cook books from 530 AD to 1950. The heating method of traditional meju bean and starch included 57 kinds of steaming, 59 of boiling, 21 of roasting + boiling, and 2 of cooking. The shape of meju included 41 kinds of egg, 27 of ball, 22 of lump, a kind of doughnut, 8 kinds of hilt, 6 of flat, 4 of chip, and a kind of square. Among the 72 gochoojang meju, the heating method of bean included 9 kinds of boiling, and 6 kinds of steaming; whereas the heating method of starch included 19 kinds of steaming of dough, 11 of rice cooking, and 5 of boiling of dough. The utensils for molding of bean meju were 49 kinds of straw sack, 14 of round straw container, 11 of heating bed, 7 of large straw bowl or Japanese-snailseed, 5 of jar, 4 of ditch, 3 of straw bowls, 2 of pottery steamer of dough, 2 of gourd, and a kind of long round bamboo bowl and sack of straw. The cover and the mat used for molding of meju included 36 kinds of straw, 17 kinds of paper mulberry leaf, 15 of wide straw seat, 14 of mugwort, 11 of pine tree leaf, 10 of soybean leaf, 6 of cocklebur leaf, 6 of sumac leaf, 6 of barley straw, 6 of mulberry leaf, 5 of fallen leaf, 5 of cogon grass, 4 of reed seat, 3 of scrap of cloth, 2 of Indian bean tree leaf, a kind of reed. There were only 5 kinds of hanging.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.239-240
• /
• 2012

With advancements in semiconductor device technologies, manufacturing processes are getting more complex and it became more difficult to maintain tighter process control. As the number of processing step increased for fabricating complex chip structure, potential fault inducing factors are prevail and their allowable margins are continuously reduced. Therefore, one of the key to success in semiconductor manufacturing is highly accurate and fast fault detection and classification at each stage to reduce any undesired variation and identify the cause of the fault. Sensors in the equipment are used to monitor the state of the process. The idea is that whenever there is a fault in the process, it appears as some variation in the output from any of the sensors monitoring the process. These sensors may refer to information about pressure, RF power or gas flow and etc. in the equipment. By relating the data from these sensors to the process condition, any abnormality in the process can be identified, but it still holds some degree of certainty. Our hypothesis in this research is to capture the features of equipment condition data from healthy process library. We can use the health data as a reference for upcoming processes and this is made possible by mathematically modeling of the acquired data. In this work we demonstrate the use of recurrent neural network (RNN) has been used. RNN is a dynamic neural network that makes the output as a function of previous inputs. In our case we have etch equipment tool set data, consisting of 22 parameters and 9 runs. This data was first synchronized using the Dynamic Time Warping (DTW) algorithm. The synchronized data from the sensors in the form of time series is then provided to RNN which trains and restructures itself according to the input and then predicts a value, one step ahead in time, which depends on the past values of data. Eight runs of process data were used to train the network, while in order to check the performance of the network, one run was used as a test input. Next, a mean squared error based probability generating function was used to assign probability of fault in each parameter by comparing the predicted and actual values of the data. In the future we will make use of the Bayesian Networks to classify the detected faults. Bayesian Networks use directed acyclic graphs that relate different parameters through their conditional dependencies in order to find inference among them. The relationships between parameters from the data will be used to generate the structure of Bayesian Network and then posterior probability of different faults will be calculated using inference algorithms.

• Applied Chemistry for Engineering
• /
• v.9 no.4
• /
• pp.565-568
• /
• 1998

Amphipathic compounds (bis-sulfonate Gemini type) with double or triple long chain alkyl groups were prepared by the reaction of N-(long chain acyl)diethanolamine diglycidyl ethers with fatty alcohols, followed by the reaction with propanesultone. All these new Gemini type surfactants were soluble in water and showed much better micelle forming ability and lowering surface tension than sodium dodecyl sulfonate with one sulfonate group. cmc and ${\Upsilon}$ cmc values of the triple-chain compounds were still much smaller than those of the corresponding double-chain compounds with two common alkyl groups. The efficiency of adsorption at the water/air interface ($pC_{20}$) of these surfactants was very high. Their foaming properties, wetting ability toward a felt chip, and lime-soap dispersing requirement (LSDR) were measured. Their initial foaming properties were high but showed good low foam stability, wettability and LSDR.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2012.11a
• /
• pp.123-123
• /
• 2012

최근 연구되고 있는 TSV(Through Silicon Via) 기술은 Si 웨이퍼 상에 직접 전기적 연결 통로인 관통홀을 형성하는 방법으로 칩간 연결거리를 최소화 할 수 있으며, 부피의 감소, 연결부 단축에 따른 빠른 신호 전달을 가능하게 한다. 이러한 TSV 기술은 최근의 초경량화와 고집적화로 대표되는 전자제품의 요구를 만족시킬 수 있는 차세대 실장법으로 기대를 모으고 있다. 한편, 납땜 재료의 주 원료인 주석은 주로 반도체 소자의 제조, 반도체 칩과 기판의 접합 및 플립 칩 (Flip Chip) 제조시의 범프 형성 등 반도체용 배선재료에 널리 사용되고 있다. 최근에는 납의 유해성 때문에 대부분의 전자제품은 무연솔더를 이용하여 제조되고 있지만, 주석을 이용한 반도체 소자가 고밀도화, 고 용량화 및 미세피치(Fine Pitch)화 되고 있기 때문에, 반도체 칩의 근방에 배치된 주석으로부터 많은 알파 방사선이 방출되어 메모리 셀의 정보를 유실시키는 소프트 에러 (Soft Error)가 발생되는 위험이 많아지고 있다. 이로 인해, 반도체 소자 및 납땜 재료의 주 원료인 주석의 고순도화가 요구되고 있으며, 특히 알파 방사선의 방출이 낮은 로우알파솔더 (Low Alpha Solder)가 요구되고 있다. 이에 따라 본 연구는 4인치 실리콘 웨이퍼상에 직경 $60{\mu}m$, 깊이 $120{\mu}m$의 비아홀을 형성하고, 비아 홀 내에 기능 박막증착 및 전해도금을 이용하여 전도성 물질인 Cu를 충전한 후 직경 $80{\mu}m$의 로우알파 Sn-1.0Ag-0.5Cu 솔더를 접합 한 후, 접합부 신뢰성 평가를 수행을 위해 고속 전단시험을 실시하였다. 비아 홀 내 미세구조와 범프의 형상 및 전단시험 후 파괴모드의 분석은 FE-SEM (Field Emission Scanning Electron Microscope)을 이용하여 관찰하였다. 연구 결과 비아의 입구 막힘이나 보이드(Void)와 같은 결함 없이 Cu를 충전하였으며, 고속전단의 경우는 전단 속도가 증가할수록 취성파괴가 증가하는 경향을 보였다. 본 연구를 통하여 전해도금을 이용한 비아 홀 내 Cu의 고속 충전 및 로우알파 솔더 볼의 범프 형성이 가능하였으며, 이로 인한 전자제품의 소프트에러의 감소가 기대된다.

• Journal of Information Management
• /
• v.42 no.3
• /
• pp.1-26
• /
• 2011

The domain of LED is analyzed for describing the current status of Korea's R&D in the domain comparing with those of others quantitatively. Fourteen sub-domains of LED manufacturing technology are selected and the time span for analysis is ten-year: 2001-2010. Bibiliometric analysis is performed by the unit of publication, core researcher, institution and country. Strategical diagram is also produced with devised two indicators: NGI and NPI. As a result, Korea is competitive in the area of Chip Scale Package, but R&D supports in another promising areas, such as large-caliber sapphire wafer, are necessary. It is also revealed that research activities are expanded dominantly in academia, but practical technologies are developed in industrial circle. It is suggested that to support core corporate and to encourage industrial-academic collaboration is essential for systematical technology development and high achievement in prominent areas.

• Journal of the Korea Society of Computer and Information
• /
• v.17 no.4
• /
• pp.1-9
• /
• 2012

As we are turnning into the aged society, accidents by falling down are increasing in the aged people's group. In this paper, we design the system with the 3-Axis acceleration sensor which is composed by a single chip. The body activity signal is measured with the signal detector and RF communicator in this proposed system and the and falling by the entering signal pattern analysis with 3-Axis acceleration sensor. For the RF communication, we are using nRF24L01p and 8bits ATmega uC for the processor. The error of energy expenditure estimation between motor driven treadmill and proposed a body activity module was 7.8% respectively. Human activities and falling is monitored according to analyze and judge the critical value of the Signal Vector. as falled down if they don't turn off the alarm after specific period and the aged person's after falling down activities are their position and more.

• Food Science and Preservation
• /
• v.11 no.2
• /
• pp.250-256
• /
• 2004

The objectives of this study were to develop a new commercial grain cooler suited to domestic weather and post-harvesting conditions for paddy, and to evaluate the performance. A prototype grain cooler capable of cooling paddy of 200 tons within 24 hours was developed. The grain cooler was designed to control the refrigeration capacity from 0 to 100% by controlling the capacity of compressor with unloading solenoid valve and by changing the flow rates of hot refrigerant gas flowing into reheater and evaporator from compressor. And a controller with one chip microprocessor was developed to control temperature and relative humidity of cooling air. The maximum cooling capacity of the grain cooler was 35,284㎉/hr at condensing/evaporating pressure of 16.5/3.6 kgf/$\textrm{cm}^2$. Maximum flow rate of cooling air was 120 ㎥/min at static pressure of 279 mmAq. The total maximum required power was 22.8㎾, and total required energy was saved from 26.7 to 33.3% of maximum power depending on operating conditions. The coefficient of performance of refrigeration devices and total coefficient of performance of the grain cooler were 4.71 and 1.8, respectively.