• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.1
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• pp.94-98
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• 2012

The behavior of ozone micro bubble cleaning system was investigated to evaluate the solution as a new method of solar cell wafer cleaning in comparison with former conventional RCA cleaning. We have developed the ozone dissolution system in the ozonated water for more efficient cleaning conditions. The optimized cleaning conditions for solar cell wafer process were 10 ppm of ozone concentration and 12 minutes in cleaning periods, respectively. We have confirmed the cleaning reliability and cell efficiencies after ozone micro bubble cleaning. Using this new cleaning technology, it was possible to obtain higher efficiency, higher productivity, and fast tact time for applying cleaning in the fields on bare ingot wafer, LED wafers as well as the solar cell wafer.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.78-83
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• 1999

The bonding interface is dependent on the properties of surfaces prior to SDB(silicon wafer direct bonding). In this paper, we prepared silicon surfaces in several chemical solutions, and annealed bonding wafers which were combined with thermally oxidized wafers and bare silicon wafers in the temperature range of $600{\times}1000^{\circ}C$. After bonding, the bonding interface is investigated by an infrared(IR) topography system which uses the penetrability of infrared through silicon wafer. Using this procedure, we observed intrinsic bubbles at elevated temperatures. So, we verified that these bubbles are related to cleaning and drying conditions, and the interface oxides on silicon wafer reduce the formation of intrinsic bubbles.

• Korean Journal of Materials Research
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• v.17 no.7
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• pp.347-351
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• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• Tribology and Lubricants
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• v.28 no.6
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• pp.272-277
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• 2012

Finite element analysis was carried out using wafer-scale and particle-scale models to understand the mechanism of the fast removal rate(edge effect) at wafer edges in the chemical-mechanical polishing process. This is the first to report that a particle-scale model can explain the edge effect well in terms of stress distribution and magnitude. The results also revealed that the mechanism could not be fully understood by using the wafer-scale model, which has been used in many previous studies. The wafer-scale model neither gives the stress magnitude that is sufficient to remove material nor indicates the coincidence between the stress distribution and the removal rate along a wafer surface.

• Proceedings of the KSME Conference
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• 2004.04a
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• pp.1082-1086
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• 2004

In silicon wafer manufacturing process, the grinding process has been adopted to improve the flatness of wafer. The grinding of wafer is usually used by the infeed grinding machine. The infeed grinding machine has been depended on imports. Therefore, it is necessary to develop the infeed grinding machine because the demand of the infeed grinding machine is increasing more and more. This paper describes the technologies of infeed grinding machine and intend to introduce the studies in the development of the intelligent grinding system for grinding of wafer. The air bearing spindle for the infeed grinding machine was developed by domestic technologies and the grinding part design of the intelligent grinding system for wafer grinding was completed.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.77-81
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• 2020

Silicon wafer etching in micro electro mechanical systems (MEMS) fabrication is challenging to form 3-D structures. Well known Si-wet etch of silicon employs potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) and sodium hydroxide (NaOH). However, the existing silicon wet etching process has a fatal disadvantage that etching of the back side of the wafer is hard to avoid. In this study, a wet etching bath for 150 mm wafers was designed to prevent back-side etching of silicon wafer, and we demonstrated the optimized process recipe to have anisotropic wet etching of silicon wafer without any damage on the backside. We also presented the design of wet bath for 300 mm wafer processing as a promising process development.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1292-1295
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• 2004

본 연구는 Cu CMP공정 중 알루미나 연마입자의 wafer 표면에서의 점착과 오염을 AFM (Atomic Force Microscopy)을 사용하여 슬러리내에서 점착력 측정과 실제 연마 후 wafer 표면의 오염을 실험적으로 비교 평가하였다. 연마입자의 adhesionn force 측정에 있어서도 역시 wafer들의 zetapotential 결과와 잘 일치하였으며, 모든 wafer 종류에 관계없이, 산성 영역에서 염기성영역의 슬러리가 적용됨에 따라 adhesion force가 작아짐을 확인할 수 있었다. 특히 FSG wafer의 zetapotential 결과는 비록 산성 분위기에서는 양성 전하값을 나타내었으나, 염기성 분위기의 pH에서는 급격하게 음성 전하값을 나타내었고, 이는 adhesionn force결과와 FESEM 결과와 잘 일치하였다.

• Journal of Korean Institute of Industrial Engineers
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• v.36 no.2
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• pp.125-137
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• 2010

This study focuses on the problem of scheduling wafer lots of several product families in the deposition workstation in a semiconductor wafer fabrication facility. There are multiple identical parallel machines in the deposition workstation, and two types of setups, record-dependent setup and family setup, may be required at the deposition machines. A record-dependent setup is needed to find optimal operational conditions for a wafer lot on a machine, and a family setup is needed between processings of different families. We suggest two-phase heuristic algorithms in which a priority-rule-based scheduling algorithm is used to generate an initial schedule in the first phase and the schedule is improved in the second phase. Results of computational tests on randomly generated test problems show that the suggested algorithms outperform a scheduling method used in a real manufacturing system in terms of the sum of weighted flowtimes of the wafer lots.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.874-877
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• 2001

SOI(Silicon-On-Insulator) technology is proposed as an alternative to bulk silicon for MEMS(Micro Electro Mechanical System) manufacturing. In this paper, we fabricated the SOI wafer with uniform active layer thickness by silicon direct bonding and mechanical polishing processes. Specially-designed electrostatic bonding system is introduced which is available for vacuum packaging and silicon-glass wafer bonding for SOG(Silicon On Glass) wafer. We demonstrated thermopile sensor and RF resonator using the SOI wafer, which has the merits of simple process and uniform membrane fabrication.

• International Journal of Precision Engineering and Manufacturing
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• v.7 no.3
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• pp.35-38
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• 2006

A study of electrowetting using an Octadecyltrichlorosilane (OTS) self-assembled monolayer (SAM) and Z- Tetraol 2000 perfluoropolyether lubricant as hydrophobic layers on Si and $SiO_2$ wafer was performed. The $SiO_2$ layer used as insulating layer was thermally grown on the silicon wafer to a thickness of 220-230 nm. The results demonstrated that the contact angle decreased from $100^{\circ}$ to $80^{\circ}$ at 28 V applied potential on $SiO_2$ wafer coated with OTS and the contact angle appeared to be reversible. However, the contact angle on the $SiO_2$ wafer coated with Z- Tetraol 2000 was not observable at 28 V applied potential. Furthermore, the contact angle on the Si wafer coated with OTS or Z- Tetraol 2000 appeared to be irreversible due to the generation of electrolysis in the droplet. It is concluded that it is feasible to use SAM as a hydrophobic layer in electrowetting applications.