• Journal of the Semiconductor & Display Technology
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• v.20 no.2
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• pp.19-24
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• 2021

As the size of semiconductor devices decreases, the etching pattern becomes very narrow and a deep high aspect ratio process becomes important. The cryogenic etching process enables high aspect ratio etching by suppressing the chemical reaction of reactive ions on the sidewall while maintaining the process temperature of -100℃. ESC is an important part for temperature control in cryogenic etching equipment. Through the cooling path inside the ESC, liquid nitrogen is used as cooling water to create a cryogenic environment. And since the ESC directly contacts the wafer, it affects the temperature uniformity of the wafer. The temperature uniformity of the wafer is closely related to the yield. In this study, the cooling path was designed and analyzed so that the wafer could have a uniform temperature distribution. The optimal cooling path conditions were obtained through the analysis of the shape of the cooling path and the change in the speed of the coolant. Through this study, by designing ESC with optimal temperature uniformity, it can be expected to maximize wafer yield in mass production and further contribute to miniaturization and high performance of semiconductor devices.

• Journal of the Semiconductor & Display Technology
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• v.20 no.4
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• pp.119-124
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• 2021

In a situation where Moore's law, which states that the performance of semiconductor integrated circuits doubles every two years, is showing a limit from a certain point, and it is difficult to increase the performance due to the limitations of exposure technology.In this study, a wafer hybrid method that can increase the degree of integration Various research on bonding technology is currently in progress. In this study, in order to achieve rotational precision between wafers in wafer hybrid bonding technology, modeling of θ_z alignment stage and VCM actuator modeling used for rotational alignment, magnetic field analysis and desgin, control, and evaluation are performed. The system of this study was controlled by VCM actuator, capactive sensor, and dspace, and the working range was ±7200 arcsec, and the in-position and resoultion were ±0.01 arcsec. The results of this study confirmed that safety and precise control are possible, and it is expected to be applied to the process to increase the integration.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.3
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• pp.19-23
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• 2015

In this study, two types of Au/TiW bump samples were fabricated by the electroplating process onto Al/Si and SiN/Si wafers for the COG (Chip On Glass) packaging. TiW was used as the UBM (Under Bump Metallurgy) material of the Au bump and it was deposited by a sputtering method under the sputtering powers ranges from 500 to 5000 Watt. We investigated the delamination phenomenas for the prepared samples as a function of the input sputtering powers. The stable interfacial adhesion condition was found to be 1500 Watt in sputtering power. In addition, the SAICAS (Surface And Interfacial Cutting Analysis System) measurement was used to find the adhesion strength of Au bumps for the prepared samples. TiW UBM films were deposited at the 1500 Watt sputtering power. As a results, there was a similar adhesion strengths between TiW/Au interfacial films on Al/Si and SiN/Si wafers. However, the adhesion strength of TiW UBM sputtering films on Al and SiN under films were 2.2 times differences, indicating 0.475 kN/m for Al/Si wafer and 0.093 kN/m for SiN/Si wafer, respectively.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.10b
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• pp.433-434
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• 2002

Chemical mechanical polishing refers to a process by which silicon and partially-processed integrated circuits (IC's) built on silicon substrates are polished to produce planar surfaces for the continued manufacturing of IC's. Chemical mechanical polishing is done by pressing the silicon wafer, face down, onto a rotating platen that is covered by a rough polyurethane pad. During rotation, the pad is flooded with a slurry that contains nanoscale particles. The pad deforms and the roughness of the surface entrains the slurry into the interface. The asperities contact the wafer and the surface is polished in a three-body abrasion process. The contact of the wafer with the 'soft' pad produces a unique elastohydrodynamic situation in which a suction force is imposed at the interface. This added force is non-uniform and can be on the order of the applied pressure on the wafer. We have measured the magnitude and spatial distribution of this suction force. This force will be described within the context of a model of the sliding of hard surfaces on soft substrates.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.26 no.10
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• pp.1406-1418
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• 2002

The direct simulation Monte Carlo(DSMC) method is employed to calculate the etch rate on Al wafer. The etchant is assumed to be Cl$_2$. The etching process of an Al wafer in a helicon plasma etcher is examined by simulating molecular collisions of reactant and product. The flow field inside a plasma etch reactor is also simulated by the DSMC method fur a chlorine feed gas flow. The surface reaction on the Al wafer is simply modelled by one-step reaction: 3C1$_2$+2Allongrightarrow1 2AIC1$_3$. The gas flow inside the reactor is compared for six different nozzle locations. It is found that the flow field inside the reactor is affected by the nozzle locations. The Cl$_2$ number density on the wafer decreases as the nozzle location moves toward the side of the reactor. Also, the present numerical results show that the nozzle location 1, which is at the top of the reactor chamber, produces a higher etch rate.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.12
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• pp.1075-1079
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• 2005

The Pseudo MOSFET measurements technique has been used for the electrical characterization of the nano SOI wafer. Silicon islands for the Pseudo MOSFET measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo MOSFET were not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device were dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100 nm SOI was obtained by thinning the silicon film of standard thick SOI wafer. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching Process dependency is greater in the thinner SOI wafer.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.5-8
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• 2009

In this paper, a high-quality low-temperature co-fired ceramic (LTCC) solenoid inductor using a solder ball and an air cavity on a silicon wafer for three-dimensional (3-D) system-in-package (SiP) is proposed. The LTCC multi-layer solenoid inductor is attached using Ag paste and solder ball on a silicon wafer with the air cavity structure. The air cavity is formed on a silicon wafer through an anisotropic wet-etching technology and is able to isolate the LTCC dielectric loss which is equivalent to a low k material effect. The electrical coupling between the metal layer and the LTCC dielectric layer is decreased by adopting the air cavity. The LTCC solenoid inductor using the solder ball and the air cavity on silicon wafer has an improved Q factor and self-resonant frequency (SRF) by reducing the LTCC dielectric resistance and parasitic capacitance. Also, 3-D device stacking technologies provide an effective path to the miniaturization of electronic systems.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.3
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• pp.205-210
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• 2000

Lead titanate thin films were fabricated on Si(100) wafer and ITO-coated glass substrates by metal organic chemical vapor deposition using ultrasonic spraying. When the ratio (Ti/Pb) of starting materials was 1.2, the films deposited on Si wafer had a single perovskite phase. The films deposited on ITO-coated glass had higher growth rate than that on Si wafer. As deposition temperature was increased from $530^{\circ}C$ to $570^{\circ}C$, dielectric constant was increased due to the increase of crystallinity and grain size. At $570^{\circ}C$, dielectric constant and dielectric loss of the films were 205 and 0.016, respectively. When the deposition temperature is higher than $600^{\circ}C$, dielectric constant was decreased.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2606-2611
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• 2003

Comprehensive study on the control system design for a RTP process has been conducted. The purpose of the control system is to maintain maximum temperature uniformity across the silicon wafer achieving precise tracking for various reference trajectories. The study has been carried out in two stages: thermal balance modeling on the basis of a semi-empirical radiation model, and optimal iterative learning controller design on the basis of a linear state space model. First, we found through steady state radiation modeling that the fourth power of wafer temperatures, lamp powers, and the fourth power of chamber wall temperature are related by an emissivity-independent linear equation. Next, for control of the MIMO system, a state space modeland LQG-based two-stage batch control technique was derived and employed to reduce the heavy computational demand in the original two-stage batch control technique. By accommodating the first result, a linear state space model for the controller design was identified between the lamp powers and the fourth power of wafer temperatures as inputs and outputs, respectively. The control system was applied to an experimental RTP equipment. As a consequence, great uniformity improvement could be attained over the entire time horizon compared to the original multi-loop PID control. In addition, controller implementation was standardized and facilitated by completely eliminating the tedious and lengthy control tuning trial.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.23-29
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• 2014

We have studied on ozonate water cleaning mechanisms to apply in manufacturing process of 156 mm silicon wafer which is used in the solar cell fabrication. We have analyzed contamination sources on wafer surface which causes poor quality and performance of products in fabrication process, and examined cleaning process using ozonate water to eliminate it. Contamination sources consist of remaining material like organic matter in slurry and detergent and particles in sawing wire. Using this novel technology it is possible for the solar cell wafer to clean with low cost, high performance, and eco-friendly.