• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 춘계학술대회 논문집
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• pp.434-437
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• 2005

Chemical Mechanical Polishing (CMP) has become an essential step in the overall semiconductor wafer fabrication technology. In general, CMP is a surface planarization method in which a silicon wafer is rotated against a polishing pad in the presence of slurry under pressure. The polishing pad, generally a polyurethane-based material, consists of polymeric foam cell walls, which aid in removal of the reaction products at the wafer interface. It has been found that the material removal rate of any polishing pad decreases due to the so-called 'pad glazing' after several wafer lots have been processed. Therefore, the pad restoration and conditioning has become essential in CMP processes to keep the urethane polishing pad at the proper friction coefficient and to allow effective slurry transport to the wafer surface. Diamond pad conditioner employs a single layer of brazed bonded diamond crystals. Due to the corrosive nature of the polishing slurry required in low pH metal CMP such as copper, it is essential to minimize the possibility of chemical interaction between very low pH slurry (pH <2) and the bond alloy. In this paper, we report an exceptional protective coated conditioner for in-situ pad conditioning in low pH Cu CMP process. The protective Cr-coated conditioner has been tested in slurry with pH levels as low as 1.5 without bond degradation.

• Current Photovoltaic Research
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• 제5권2호
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• pp.59-62
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• 2017

Surface texturing is affected the uniformity and size of pyramid with saw mark defect density. To analysis the influence of the saw mark defect density, we textured various si wafer. When the texturing process proceeds without the saw mark removal, silicon wafer of low-saw mark defect density showed small pyramid size of $3.5{\mu}m$ with the lowest average value of the reflectance of 10.6%. When texturing carried out after removal of the saw mark using the TMAH solution, we obtained a reflectance of about 11% and the large pyramid size of $5{\mu}m$. As a result, saw mark wafers showed a better pyramid structure than saw mark-free wafer. This result showed that saw mark can take place more smooth etching by the KOH solution and saw mark-free wafer is determined to be a factor that have a higher reflectance and a large pyramid.

• 제어로봇시스템학회논문지
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• 제6권1호
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• pp.104-111
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• 2000

A fuzzy logic Run-by-Run(RbR) controller and an in -line wafer characteristics prediction scheme for the rapid thermal processing system have been developed for the study of process repeatability. The fuzzy logic RbR controller provides a framework for controlling a process which is subject to disturbances such as shifts and drifts as a normal part of its operation. The fuzzy logic RbR controller combines the advantages of both fuzzy logic and feedback control. It has two components : fuzzy logic diagnostic system and model modification system. At first, a neural network model is constructed with the I/O data collected during the designed experiments. The wafer state after each run is assessed by the fuzzy logic diagnostic system with featuring step. The model modification system updates the existing neural network process model in case of process shift or drift, and then select a new recipe based on the updated model using genetic algorithm. After this procedure, wafer characteristics are predicted from the in-line wafer characteristics prediction model with principal component analysis. The fuzzy logic RbR controller has been applied to the control of Titanium SALICIDE process. After completing all of the above, it follows that: 1) the fuzzy logic RbR controller can compensate the process draft, and 2) the in-line wafer characteristics prediction scheme can reduce the measurement cost and time.

• 한국시뮬레이션학회논문지
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• 제15권2호
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• pp.51-57
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• 2006

현재 반도체 산업은 200mm 웨이퍼에서 300mm 웨이퍼 공정으로 기술이 변화하고 있다. 300mm 웨이퍼 제조업체들은 Fabrication Line (FAB Line) 자동화를 비용절감 실현의 방책으로 사용하고 있다. 또한 기술의 확산, 시장 경쟁력의 격화 등으로 생산성 향상에 의한 원가절감이 반도체 산업 성장의 근본요인이 되고 있다. 대부분의 반도체 업체들은 생산성을 높이기 위해 average cycle time을 줄이는데 총력을 기울이고 있다. 본 논문에서는 average cycle time을 줄이는 데 중점을 두고, 300mm 반도체 제조공정을 시뮬레이션 하였다.

• 마이크로전자및패키징학회지
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• 제16권1호
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• pp.27-31
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• 2009

본 논문에서는 웨이퍼 레벨 기술을 이용한 CIS용 폴리머 접합 기술을 연구하고 접합 후의 warpage 분석과 개별 패키지의 신뢰성 테스트를 수행하였다. 균일한 접합 높이를 유지하기 위하여 glass 웨이퍼 상에 dam을 형성하고 접합용 폴리머 층을 patterning하여 Si과 glass 웨이퍼의 접합 테스트를 수행하였다. Si 웨이퍼의 접합온도, 접합 압력 그리고 접합 층이 낮을수록 warpage 결과가 감소하였으며 접합시간과 승온 시간이 짧을수록 warpage 결과가 증가하는 것을 확인하였다. 접합 된 웨이퍼를 dicing 하여 각 개별 칩 단위로 TC, HTC, Humidity soak의 신뢰성 테스트를 수행하였으며 warpage 결과가 패키지의 신뢰성 결과에 미치는 영향은 미비한 것으로 확인되었다.

• 한국산학기술학회:학술대회논문집
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• 한국산학기술학회 2004년도 춘계학술대회
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• pp.50-53
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• 2004

본 논문에서는 Si wafer와 Cu사이의 밀착력을 증가시키기 위해 Si wafer전처리 후 plasma와 SAMs처리 방법에 의한 Cu도금의 형성에 관한 방법을 설명하였다. Si wafer를 Piranha solution과 $0.5\%$ HF처리 후 유기박막인 SAMs과 plasma를 이용하는 방법으로 wafer와 Cu층 사이의 밀착력을 증가시켰다. 도금층의 밀착력은 scratch test 로 측정하였으며, AEM을 이용해 시편에 형성된 패턴의 형태를 관찰하고 SEM과 EDS를 이용해 시편의 조직을 관찰하였다. 그 결과 Si wafer를 O2, He, SAMs를 혼합처리 했을 때 밀착성이 가장 우수하였다.

• 한국재료학회지
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• 제15권9호
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• pp.613-619
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• 2005

The ever increasing popularity and acceptance in the market place of portable systems, such as cell phones, PDA, notebook PC, etc., are fueling effects in further miniaturizing and lowering power consumption in these systems. The dynamic power consumption due to the CPU activities and the static power consumption due to leakage currents are two major sources of power consumption. Smaller devices and a lower de voltage lead to reducing the power requirement, while better insulation and isolation of devices lead to reducing leakage currents. All these can be harnessed in the SOI (silicon-on-insulator) technology. In this study, the key aspects of the SOI technology, mainly device electrical properties and device processing steps, are briefly reviewed. The interesting materials issues, such as SOI structure formation and SOI wafer fabrication methods, are then surveyed. In particular, the recent technological innovations in two major SOI wafer fabrication methods, namely wafer bonding and SIMOX, are explored and compared in depth. The results of the study are nixed in that, although the quality of the SOI structures has shown great improvements, the processing steps are still found to be too complex. Between the two methods, no clear winner has yet emerged in terms of the product quality and cost considerations.

• 한국레이저가공학회지
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• 제6권3호
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• pp.29-35
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• 2003

In semiconductor processing, there are two types of particle contaminated onto the wafer, i.e. dry and wet state particles. In order to evaluate the cleaning performance of laser shock wave cleaning method, the removal of 1 m sized alumina particle at different particle conditions from silicon wafer has been carried out by laser-induced shock waves. It was found that the removal efficiency by laser shock cleaning was strongly dependent on the particle condition, i.e. the removal efficiency of dry alumina particle from silicon wafer was around 97％ while the efficiencies of wet alumina particle in DI water and IPA are 35％ and 55％ respectively. From the analysis of adhesion forces between the particle and the silicon substrate, the adhesion force of the wet particle where capillary force is dominant is much larger than that of the dry particle where Van der Waals force is dominant. As a result, it is seen that the particle in wet condition is much more difficult to remove from silicon wafer than the particle in dry condition by using physical cleaning method such as laser shock cleaning.

• 한국산학기술학회논문지
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• 제5권5호
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• pp.458-461
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• 2004

본 논문에서는 Si wafer와 Cu사이의 밀착력을 증가시키기 위해 Si wafer전처리 후 plasma와 SAMs처리 방법에 의한 Cu도금의 형성에 관한 방법을 설명하였다. Si wafer를 Piranha solution과 $0.5{\%}$ HF처리 후 유기박막인 SAMs과 plasma를 이용하는 방법으로 wafer와 Cu층 사이의 밀착력을 증가시켰다. 도금층의 밀착력은 scratch test 로 측정하였으며 , AFM을 이용해 시편에 형성된 패턴의 형태를 관찰하고 SEM과 EDS를 이용해 시편의 조직을 관찰하였다. 그 결과 Si wafer를 $O_{2}, He, SAMs$를 혼합처리 했을 때 밀착성이 가장 우수하였다.

• 반도체디스플레이기술학회지
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• 제16권3호
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• pp.41-46
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• 2017

This study aims to select suitable co-solvents and to obtain optimal process conditions in order to improve process efficiency and productivity through experimental results obtained under various experimental conditions for the etching and rinsing process using liquid carbon dioxide and supercritical carbon dioxide. Acetone was confirmed to be effective through basic experiments and used as the etching solution for MEMS-wafer etching in this study. In the case of using liquid carbon dioxide as the solvent and acetone as the etching solution, these two components were not mixed well and showed a phase separation. Liquid carbon dioxide in the lower layer interfered with contact between acetone and Mems-wafer during etching, and the results after rinsing and drying were not good. Based on the results obtained under various experimental conditions, the optimum process for treating MEMS-wafer using supercritical CO2 as the solvent, acetone as the etching solution, and methanol as the rinsing solution was set up, and MEMS-wafer without stiction can be obtained by continuous etching, rinsing and drying process. In addition, the amount of the etching solution (acetone) and the cleaning liquid (methanol) compared to the initial experimental values can be greatly reduced through optimization of process conditions.