• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.6
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• pp.80-85
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• 2019

Vanadium dioxide is a well-known metal-insulator phase transition material. Lots of researches of vanadium redox flow batteries have been researched as large scale energy storage system. In this study, vanadium oxide($VO_x$) thin films were applied to cathode for lithium ion battery. The $VO_x$ thin films were deposited on Si substrate($SiO_2$ layer of 300 nm thickness was formed on Si wafer via thermal oxidation process), quartz substrate by RF magnetron sputter system for 60 minutes at $500^{\circ}C$ with different RF powers. The surface morphology of as-deposited $VO_x$ thin films was characterized by field-emission scanning electron microscopy. The crystallographic property was confirmed by Raman spectroscopy. The optical properties were characterized by UV-visible spectrophotometer. The coin cell lithium-ion battery of CR2032 was fabricated with cathode material of $VO_x$ thin films on Cu foil. Electrochemical property of the coin cell was investigated by electrochemical analyzer. As the results, as increased of RF power, grain size of as-deposited $VO_x$ thin films was increased. As-deposited thin films exhibit $VO_2$ phase with RF power of 200 W above. The transmittance of as-deposited $VO_x$ films exhibits different values for different crystalline phase. The cyclic performance of $VO_x$ films exhibits higher values for large surface area and mixed crystalline phase.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.4
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• pp.497-502
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• 2019

Metal oxide nanostructures are promising materials for advanced applications, such as high sensitive gas sensors, and high capacitance lithium-ion batteries. In this study, tin oxide (SnO) nanostructures were grown on a Si wafer substrate using a two-zone horizontal furnace system for a various substrate temperatures. The raw material of tin dioxide ($SnO_2$) powder was vaporized at $1070^{\circ}C$ in an alumina crucible. High purity Ar gas, as a carrier gas, was flown with a flow rate of 1000 standard cubic centimeters per minute. The SnO nanostructures were grown on a Si substrate at $350{\sim}450^{\circ}C$ under 545 Pa for 30 minutes. The surface morphology of the as-grown SnO nanostructures on Si substrate was characterized by field-emission scanning electron microscopy (FE-SEM) and atomic force microscopy (AFM). Raman spectroscopy was used to confirm the phase of the as-grown SnO nanostructures. As the results, the as-grown tin oxide nanostructures exhibited a pure tin monoxide phase. As the substrate temperature was increased from $350^{\circ}C$ to $424^{\circ}C$, the thickness and grain size of the SnO nanostructures were increased. The SnO nanostructures grown at $450^{\circ}C$ exhibited complex polycrystalline structures, whereas the SnO nanostructures grown at $350^{\circ}C$ to $424^{\circ}C$ exhibited simple grain structures parallel to the substrate.

• Applied Chemistry for Engineering
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• v.33 no.6
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• pp.630-635
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• 2022

Copper(II) oxide (CuO), electroless plated on a nitrogen-containing carbon sponge prepared by a melamine sponge thermal treatment, was developed as a nitric oxide (NO) gas sensor that operates without a wafer. The CuO content on the surface of the carbon sponge increased as the plating time increased, but the content of nitrogen known to induce NO gas adsorption decreased. The untreated carbon sponge showed a maximum resistance change (5.0%) at 18 min. On the other hand, the CuO plated sample (CuO30s-CS) showed a maximum resistance change of 18.3% in 8 min. It is considered that the improvement of the NO gas sensing capability was caused by the increase in hole carriers of the carbon sponge and improved movement of electrons due to CuO. However, the NO gas detection resistance of the CuO electroless plated carbon sponge for 60 s decreased to 1.9%. It is considered that the surface of the carbon sponge was completely plated with CuO, resulting in a decrease in the NO gas adsorption capacity and resistance change. Thus, CuO-plated carbon sponge can be used as an effective NO gas sensor because it has fast and excellent resistance change properties, but CuO should not be completely plated on the surface of the carbon sponge.

• Journal of Conservation Science
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• v.36 no.6
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• pp.511-518
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• 2020

There have been reports that the "jeongcho (定礎)" letters of the foundation stone at the historical site No. 280 of the "Main Building of the Bank of Korea in Seoul" were written by Prince Ito Hirobumi (伊藤博文), the first Resident-General of Japan in Korea. An on-site investigation by an advisory group consisting of three experts in calligraphy; revealed that the two characters of '定礎' inscribed on the foundation stone are the characteristics of Ito Hirobumi's handwriting, judging from the writing style and habits observed in the collections of the Central Library of Hamamatsu City, Japan. It was reported that his writing was confirmed by the experts, but no basis was provided. To provide more objective and quantitative supporting data, rather than qualitative judgment based on feeling, it is necessary to present the basis for judgment through quantitative image comparison results through image analysis. In this paper, using image analysis software, Ito Hirobumi's calligraphy writing and the inscribed characters of the foundation stone were compared and analyzed to confirm the contents of the press release. The character comparison process and character area measurement results are a good example showing that if objective judgment basis data are needed in a similar situation, an objective judgment basis can be prepared through quantification using image analysis.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1281-1286
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• 2006

We have used the silicon-carbide(4H-SiC) instead of conventional silicon materials to develope of the planar junction barrier schottky rectifier for ultra high breakdown voltage(1,200 V grade). The substrate size is 2 inch wafer, Its concentration is $3*10^{18}/cm^{3}$ of $n^{+}-$type, thickness of epitaxial layer $12{\mu}m$ conentration is $5*10^{15}cm^{-3}$ of n-type. The fabticated devices are junction barrier schottky rectifier, The guard ring for improvement of breakdown voltage is designed by the box-like impurity of boron, the width and space of guard ring was designed by variation. The contact metals to rectify were used by the $Ni(3,000\:{\AA})/Au(2,000\:{\AA})$. As a results, the on-state voltage is 1.26 V, on-state resistance is $45m{\Omega}/cm^{3}$, maximum value of improved reverse breakdown voltage is 1180V, reverse leakage current density is $2.26*10^{-5}A/CM^{3}$. We had improved the measureme nt results of the electrical parameters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.1-8
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• 2011

One of the most important parameters that limit maximum output power of transistor is breakdown. InAlAs/InGaAs/GaAs Metamorphic HEMTs (MHEMTs) have some advantages, especially for cost, compared with InP-based ones. However, GaAs-based MHEMTs and InP-based HEMTs are limited by lower breakdown voltage for output power even though they have good microwave and millimeter-wave frequency performance with lower minimum noise figure. In this paper, InAlAs/$In_xGa_{1-x}As$/GaAs MHEMTs are simulated and analyzed for breakdown. The parameters affecting breakdown are investigated in the fabricated 0.1-${\mu}m$ ${\Gamma}$-gate MHEMT device having the modulation-doped $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}As$ heterostructure on the GaAs wafer using the hydrodynamic transport model of a 2D commercial device simulator. The impact ionization and gate field effect in the fabricated device including deep-level traps are analyzed for breakdown. In addition, Indium mole-fraction-dependent impact ionization rates are proposed empirically for $In_{0.52}Al_{0.48}As/In_xGa_{1-x}As$/GaAs MHEMTs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.456-456
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• 2009

Boron doping on an n-type Si wafer is requisite process for IBC (Interdigitated Back Contact) solar cells. Fiber laser annealing is one of boron doping methods. For the boron doping, uniformly coated or deposited film is highly required. Plasma enhanced chemical vapor deposition (PECVD) method provides a uniform dopant film or layer which can facilitate doping. Because amorphous silicon layer absorption range for the wavelength of fiber laser does not match well for the direct annealing. In this study, to enhance thermal affection on the existing p-a-Si:H layer, a ${\mu}c$-Si:H intrinsic layer was deposited on the p-a-Si:H layer additionally by PECVD. To improve heat transfer rate to the amorphous silicon layer, and as heating both sides and protecting boron eliminating from the amorphous silicon layer. For p-a-Si:H layer with the ratio of $SiH_4$ : $B_2H_6$ : $H_2$ = 30 : 30 : 120, at $200^{\circ}C$, 50 W, 0.2 Torr for 30 minutes, and for ${\mu}c$-Si:H intrinsic layer, $SiH_4$ : $H_2$ = 10 : 300, at $200^{\circ}C$, 30 W, 0.5 Torr for 60 minutes, 2 cm $\times$ 2 cm size wafers were used. In consequence of comparing the results of lifetime measurement and sheet resistance relation, the laser condition set of 20 ~ 27 % of power, 150 ~ 160 kHz, 20 ~ 50 mm/s of marking speed, and $10\;{\sim}\;50 {\mu}m$ spacing with continuous wave mode of scanner lens showed the correlation between lifetime and sheet resistance as $100\;{\Omega}/sq$ and $11.8\;{\mu}s$ vs. $17\;{\Omega}/sq$ and $8.2\;{\mu}s$. Comparing to the singly deposited p-a-Si:H layer case, the additional ${\mu}c$-Si:H layer for doping resulted in no trade-offs, but showed slight improvement of both lifetime and sheet resistance, however sheet resistance might be confined by the additional intrinsic layer. This might come from the ineffective crystallization of amorphous silicon layer. For the additional layer case, lifetime and sheet resistance were measured as $84.8\;{\Omega}/sq$ and $11.09\;{\mu}s$ vs. $79.8\;{\Omega}/sq$ and $11.93\;{\mu}s$. The co-existence of $n^+$layeronthesamesurfaceandeliminating the laser damage should be taken into account for an IBC solar cell structure. Heavily doped uniform boron layer by fiber laser brings not only basic and essential conditions for the beginning step of IBC solar cell fabrication processes, but also the controllable doping concentration and depth that can be established according to the deposition conditions of layers.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.4
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• pp.23-29
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• 2000

We demonstrate the fabrication method of high-density and high-quality solder bump solving a copper (Cu) cross-contamination in Si-LSI laboratory. The Cu cross-contamination is solved by separating solder-bump process by two steps. Former is via-formation process excluding Cu/Ti under ball metallurgy (UBM) layer sputtering in Si-LSI laboratory. Latter is electroplating process including Ti-adhesion and Cu-seed layers sputtering out of Si-LSI laboratory. Thick photoresist (PR) is achieved by a multiple coating method. After TiW/Al-electrode sputtering for electroplating and via formation in Si-LSI laboratory, Cu/Ti UBM layer is sputtered on sample. The Cu-seed layer on the PR is etched during Cu-electroplating with low-electroplating rate due to a difference in resistance of UBM layer between via bottom and PR. Therefore Cu-buffer layer can be electroplated selectively at the via bottom. After etching the Ti-adhesion layer on the PR, Sn/Pb solder layer with a composition of 60/40 is electroplated using a tin-lead electroplating bath with a metal stoichiometry of 60/40 (weight percent ratio). Scanning electron microscope image shows that the fabricated solder bump is high-uniformity and high-quality as well as symmetric mushroom shape. The solder bumps with even 40/60 $\mu\textrm{m}$ in diameter/pitch do not touch during electroplating and reflow procedures. The solder-bump process of high-uniformity and high-density with the Cu cross-contamination free in Si-LSI laboratory will be effective for electronic microwave application.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.33-38
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• 2001

We investigate the via-size dependance of as-electroplated- and reflow-bump shapes for realizing both high-density and high-aspect ratio of solder bump. The solder bump is fabricated by subsequent processes as follows. After sputtering a TiW/Al electrode on a 5-inch Si-wafer, a thick photoresist for via formation it obtained by multiple-codling method and then vias with various diameters are defined by a conventional photolithography technique using a contact alinger with an I-line source. After via formation the under ball metallurgy (UBM) structure with Ti-adhesion and Cu-seed layers is sputtered on a sample. Cu-layer and Sn/pb-layer with a competition ratio of 6 to 4 are electroplated by a selective electroplating method. The reflow-bump diameters at bottom are unchanged, compared with as-electroplated diameters. As-electroplated- and reflow-bump shapes, however, depend significantly on the via size. The heights of as-electroplated and reflow bumps increase with the larger cia, while the aspect ratio of bump decreases. The nearest bumps may be touched by decreasing the bump pitch in order to obtain high-density bump. The touching between the nearest bumps occurs during the overplating procedure rather than the reflowing procedure because the mushroom diameter formed by overplating is larger than the reflow-bump diameter. The arrangement as zig-zag rows can be effective for realizing the flip-chip-interconnect bump with both high-density and high-aspect ratio.

• Korean Chemical Engineering Research
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• v.44 no.5
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• pp.513-519
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• 2006

We developed two kinds of the microchip for application to electrophoresis based on both glass and quartz employing the MEMS fabrications. The poly-Si layer deposited onto the bonding interface apart from channel regions can play a role as the optical slit cutting off the stray light in order to concentrate the UV ray, from which it is possible to improve the signal-to-noise (S/N) ratio of the detection on a chip. In the glass chip, the deposited poly-Si layer had an important function of the etch mask and provided the bonding surface properly enabling the anodic bonding. The glass wafer including more impurities than quartz one results in the higher surface roughness of the channel wall, which affects subsequently on the microflow behavior of the sample solutions. In order to solve this problem, we prepared here the mixed etchant consisting HF and $NH_4F$ solutions, by which the surface roughness was reduced. Both the shape and the dimension of each channel were observed, and the electroosmotic flow velocities were measured as 0.5 mm/s for quartz and 0.36 mm/s for glass channel by implementing the microchip electrophoresis. Applying the optical slit with poly-Si layer provides that the S/N ratio of the peak is increased as ca. 2 times for quartz chip and ca. 3 times for glass chip. The maximum UV absorbance is also enhanced with ca. 1.6 and 1.7 times, respectively.