• Journal of the Korean Society for Nondestructive Testing
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• v.27 no.5
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• pp.375-382
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• 2007

Nondestructive testing (NDT) by using the electromagnetic methods are useful for detecting cracks on the surface and subsurface of the metal. However, when the material contains both ferromagnetic and paramagnetic materials, it is difficult for NDT to detect and analyze cracks using this method. In addition the existence of a partial ferromagnetic material can be incorrectly characterized as a crack in the several cases. On the other hand a large crack has sometimes been misunderstood as a partially magnetized region. Inconel 600 is an important material in atomic energy plant. A nickel film is coated when a crack a appears on an Inconel substrate. Cracks are difficult to detect on the combined material of an Inconel substrate with a nickel film, which are paramagnetic and ferromagnetic material respectively. In this paper, a scan type magnetic camera, which uses a complex induced current-magnetic flux leakage (CIC-MFL) method as a magnetic source and a linearly integrated Hall sensor array (LIHaS) on a wafer as the magnetic sensors, was examined for its ability to detect cracks on the combined material. The evaluation probability of a crack is discussed. In addition the detection probability of the minimum depth was reported.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.264-264
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• 2010

Single-walled carbon nanotubes (SWCNTs) were grown on a Si wafer by using thermal chemical vapor deposition (t-CVD). We investigated the effect of the catalyst deposition rate on the types of CNTs grown on the substrate. In general, smaller islands of catalyst occur by agglomeration of a catalyst layer upon annealing as the catalyst layer becomes thinner, which results in the growth of CNTs with smaller diameters. For the same thickness of catalyst, a slower deposition rate will cause a more uniformly thin catalyst layer, which will be agglomerated during annealing, producing smaller catalyst islands. Thus, we can expect that the smaller-diameter CNTs will grow on the catalyst deposited with a lower rate even for the same thickness of catalyst. The 0.5-nm-thick Fe served as a catalyst, underneath which Al was coated as a catalyst support as well as a diffusion barrier on the Si substrate. The catalyst layers were. coated by using thermal evaporation. The deposition rates of the Al and Fe layers varied to be 90, 180 sec/nm and 70, 140 sec/nm, respectively. We prepared the four different combinations of the deposition rates of the AI and Fe layers. CNTs were synthesized for 10 min by flowing 60 sccm of Ar and 60 sccm of $H_2$ as a carrier gas and 20 sccm of $C_2H_2$ as a feedstock at 95 torr and $810^{\circ}C$. The substrates were subject to annealing for 20 sec for every case to form small catalyst islands prior to CNT growth. As-grown CNTs were characterized by using field emission scanning electron microscopy, high resolution transmission electron microscopy, Raman spectroscopy, UV-Vis NIR spectroscopy, and atomic force microscopy. The fast deposition of both the Al and Fe layers gave rise to the growth of thin multiwalled CNTs with the height of ${\sim}680\;{\mu}m$ for 10 min while the slow deposition caused the growth of ${\sim}800\;{\mu}m$ high SWCNTs. Several radial breathing mode (RBM) peaks in the Raman spectra were observed at the Raman shifts of $113.3{\sim}281.3\;cm^{-1}$, implying the presence of SWCNTs (or double-walled CNTs) with the tube diameters 2.07~0.83 nm. The Raman spectra of the as-grown SWCNTs showed very low G/D peak intensity ratios, indicating their low defect concentrations.

• Current Photovoltaic Research
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• v.9 no.3
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• pp.75-83
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• 2021

The tunnel oxide passivated contact (TOPCon) structure got more consideration for development of high performance solar cells by the introduction of a tunnel oxide layer between the substrate and poly-Si is best for attaining interface passivation. The quality of passivation of the tunnel oxide layer clearly depends on the bond of SiO in the tunnel oxide layer, which is affected by the subsequent annealing and the tunnel oxide layer was formed in the suboxide region (SiO, Si₂O, Si₂O₃) at the interface with the substrate. In the suboxide region, an oxygen-rich bond is formed as a result of subsequent annealing that also improves the quality of passivation. To control the surface morphology, annealing profile, and acceleration rate, an oxide tunnel junction structure with a passivation characteristic of 700 mV or more (V_oc) on a p-type wafer could achieved. The quality of passivation of samples subjected to RTP annealing at temperatures above 900℃ declined rapidly. To improve the quality of passivation of the tunnel oxide layer, the physical properties and thermal stability of the thin layer must be considered. TOPCon silicon solar cell has a boron diffused front emitter, a tunnel-SiO_x/n⁺-poly-Si/SiN_x:H structure at the rear side, and screen-printed electrodes on both sides. The saturation currents J_o of this structure on polished surface is 1.3 fA/cm² and for textured silicon surfaces is 3.7 fA/cm² before printing the silver contacts. After printing the Ag contacts, the J_o of this structure increases to 50.7 fA/cm² on textured silicon surfaces, which is still manageably less for metal contacts. This structure was applied to TOPCon solar cells, resulting in a median efficiency of 23.91%, and a highest efficiency of 24.58%, independently. The conversion efficiency of interdigitated back-contact solar cells has reached up to 26% by enhancing the optoelectrical properties for both-sides-contacted of the cells.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.32 no.2
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• pp.103-108
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• 2019

Non-equilibrium molecular dynamics simulation on the thermal boundary resistance(TBR) of an aluminum(Al)/silicon(Si) interface was performed in the present study. The constant heat flux across the Si/Al interface was simulated by adding the kinetic energy in hot Si region and removing the same amount of the energy from the cold Al region. The TBR estimated from the sharp temperature drop at the interface was independent of heat flux and equal to $5.13{\pm}0.17K{\cdot}m^2/GW$ at 300K. The simulation result was experimentally confirmed by the time-domain thermoreflectance technique. A 90nm thick Al film was deposited on a Si(100) wafer using an e-beam evaporator and the TBR on the film/substrate interface was measured using the time-domain thermoreflectance technique based on a femtosecond laser system. A numerical solution of the transient heat conduction equation was obtained using the finite difference method to estimate the TBR value. Experimental results were compared to the prediction and discussions on the nanoscale thermal transport phenomena were made.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.406-406
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• 2016

To get high efficiency n-type crystalline silicon solar cells, passivation is one of the key factor. Tunnel oxide (SiO2) reduce surface recombination as a passivation layer and it does not constrict the majority carrier flow. In this work, the passivation quality enhanced by different chemical solution such as HNO3, H2SO4:H2O2 and DI-water to make thin tunnel oxide layer on n-type crystalline silicon wafer and changes of characteristics by subsequent annealing process and firing process after phosphorus doped amorphous silicon (a-Si:H) deposition. The tunneling of carrier through oxide layer is checked through I-V measurement when the voltage is from -1 V to 1 V and interface state density also be calculated about $1{\times}1012cm-2eV-1$ using MIS (Metal-Insulator-Semiconductor) structure . Tunnel oxide produced by 68 wt% HNO3 for 5 min on $100^{\circ}C$, H2SO4:H2O2 for 5 min on $100^{\circ}C$ and DI-water for 60 min on $95^{\circ}C$. The oxide layer is measured thickness about 1.4~2.2 nm by spectral ellipsometry (SE) and properties as passivation layer by QSSPC (Quasi-Steady-state Photo Conductance). Tunnel oxide layer is capped with phosphorus doped amorphous silicon on both sides and additional annealing process improve lifetime from $3.25{\mu}s$ to $397{\mu}s$ and implied Voc from 544 mV to 690 mV after P-doped a-Si deposition, respectively. It will be expected that amorphous silicon is changed to poly silicon phase. Furthermore, lifetime and implied Voc were recovered by forming gas annealing (FGA) after firing process from $192{\mu}s$ to $786{\mu}s$. It is shown that the tunnel oxide layer is thermally stable.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.6
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• pp.709-714
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• 2018

This study researched the reasons for changing polarity in accordance with junction properties in an interface of semiconductors. The contact properties of semiconductors are related to the effect of the semiconductor's device. Therefore, it is an important factor for understanding the junction characteristics in the semiconductor to increase the efficiency of devices. For generation of various junction properties, carbon-doped silicon oxide (SiOC) was deposited with various argon (Ar) gas flow rates, and the characteristics of the SiOC was varied based on the polarity in accordance with the Ar gas flows. Tin-doped zinc oxide (ZTO) as the conductor was deposited on the SiOC as an insulator to research the conductivity. The properties of the SiOC were determined from the formation of a depletion layer by the ionization reaction with various Ar gas flow rates due to the plasma energy. Schottky contact was good in the condition of the depletion layer, with a high potential barrier between the silicon (Si) wafer and the SiOC. The rate of ionization reactions increased when increasing the Ar gas flow rate, and then the potential barrier of the depletion layer was also increased owing to deficient ions from electron-hole recombination at the junction. The dielectric properties of the depletion layer changed to the properties of an insulator, which is favorable for Schottky contact. When the ZTO was deposited on the SiOC with Schottky contact, the stability of the ZTO was improved by the ionic recombination at the interface between the SiOC and the ZTO. The conductivity of ZTO/SiOC was also increased on SiOC film with ideal Schottky contact, in spite of the decreasing charge carriers. It increases the demand on the Schottky contact to improve the thin semiconductor device, and this study confirmed a high-performance device owing to Schottky contact in a low current system. Finally, the amount of current increased in the device owing to ideal Schottky contact.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.26 no.3
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• pp.270-280
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• 2016

This paper investigates the evolution of EM admittance of piezoelectric transducers mounted on a notched beam from wave propagation perspective. A finite element analysis is adopted to obtain numerical solutions for Lamb waves reverberating on the notched beam. The mode-converted Lamb wave signals due to a notch are extracted by using the polarization characteristics of piezoelectric transducers collocated on the beam. Then, a series of temporal spectrums are computed to demonstrate the evolution of EM admittance through fast Fourier transform of the mode-converted Lamb wave signals which are consecutively truncated in the time domain. When truncation time is relatively small, the corresponding temporal spectrum is governed by the characteristics of the input driving frequency. As truncation time becomes large, however, the modal characteristics of the notched beam play a crucial role in the temporal spectrum within the input driving frequency band. This implies that mode-converted Lamb waves reverberating on the beam contributes to the resonance of the beam. The root mean square values are computed for the temporal spectrums in the vicinity of each resonance frequency. The root mean square values increase monotonically with respect to truncation time for any resonance frequencies. Finally the implications of the numerical observation are discussed in the context of damage detection of a beam.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Corrosion Science and Technology
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• v.9 no.6
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• pp.276-280
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• 2010

Copper(Cu) as an interconnecting metal layer can replace aluminum (Al) in IC fabrication since Cu has low electrical resistivity, showing high immunity to electromigration compared to Al. However, it is very difficult for copper to be patterned by the dry etching processes. The chemical mechanical polishing (CMP) process has been introduced and widely used as the mainstream patterning technique for Cu in the fabrication of deep submicron integrated circuits in light of its capability to reduce surface roughness. But this process leaves a large amount of residues on the wafer surface, which must be removed by the post-CMP cleaning processes. Copper corrosion is one of the critical issues for the copper metallization process. Thus, in order to understand the copper corrosion problems in post-CMP cleaning solutions and study the effects of DC biases and post-CMP cleaning solution concentrations on the Cu film, a constant voltage was supplied at various concentrations, and then the output currents were measured and recorded with time. Most of the cases, the current was steadily decreased (i.e. resistance was increased by the oxidation). In the lowest concentration case only, the current was steadily increased with the scarce fluctuations. The higher the constant supplied DC voltage values, the higher the initial output current and the saturated current values. However the time to be taken for it to be saturated was almost the same for all the DC supplied voltage values. It was indicated that the oxide formation was not dependent on the supplied voltage values and 1 V was more than enough to form the oxide. With applied voltages lower than 3 V combined with any concentration, the perforation through the oxide film rarely took place due to the insufficient driving force (voltage) and the copper oxidation ceased. However, with the voltage higher than 3 V, the copper ions were started to diffuse out through the oxide film and thus made pores to be formed on the oxide surface, causing the current to increase and a part of the exposed copper film inside the pores gets back to be oxidized and the rest of it was remained without any further oxidation, causing the current back to decrease a little bit. With increasing the applied DC bias value, the shorter time to be taken for copper ions to be diffused out through the copper oxide film. From the discussions above, it could be concluded that the oxide film was formed and grown by the copper ion diffusion first and then the reaction with any oxidant in the post-CMP cleaning solution.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.137-137
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• 2009

Thin-film transistors (TFTs) that can be prepared at low temperatures have attracted much attention due to the great potential for flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited by low field effect mobility or rapidly degraded after exposing to air in many cases. Another approach is amorphous oxide semiconductors. Amorphous oxide semiconductors (AOSs) have exactly attracted considerable attention because AOSs were fabricated at room temperature and used lots of application such as flexible display, electronic paper, large solar cells. Among the various AOSs, a-IGZO was considerable material because it has high mobility and uniform surface and good transparent. The high mobility is attributed to the result of the overlap of spherical s-orbital of the heavy pest-transition metal cations. This study is demonstrated the effect of thickness channel layer from 30nm to 200nm. when the thickness was increased, turn on voltage and subthreshold swing were decreased. a-IGZO TFTs have used a shadow mask to deposit channel and source/drain(S/D). a-IGZO were deposited on SiO2 wafer by rf magnetron sputtering. using power is 150W, working pressure is 3m Torr, and an O2/Ar(2/28 SCCM) atmosphere at room temperature. The electrodes were formed with Electron-beam evaporated Ti(30nm) and Au(70nm) structure. Finally, Al(150nm) as a gate metal was evaporated. TFT devices were heat treated in a furnace at $250^{\circ}C$ in nitrogen atmosphere for an hour. The electrical properties of the TFTs were measured using a probe-station to measure I-V characteristic. TFT whose thickness was 150nm exhibits a good subthreshold swing(S) of 0.72 V/decade and high on-off ratio of 1E+08. Field effect mobility, saturation effect mobility, and threshold voltage were evaluated 7.2, 5.8, 8V respectively.