• Journal of Korea Foundry Society
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• v.33 no.4
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• pp.157-161
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• 2013

A ribbon-type polycrystalline silicon wafer was directly fabricated from liquid silicon via a novel technique for both a fast growth rate and large grain size by exploiting gas pressure. Effects of processing parameters such as moving speed of a dummy bar and the length of the solidification zone on continuous casting of the silicon wafer were investigated. Silicon melt extruded from the growth region in the case of a solidification zone with a length of 1cm due to incomplete solidification. In case of a solidification zone wieh a length of 2 cm, on the other hand, continuous casting of the wafer was impossible due to the volume expansion of silicon derived from the liquid-solid transformation in solidification zone. Consequently, the optimal length of the solidification zone was 1.5 cm for maintaining the position of the solid-liquid interface in the solidification zone. The silicon wafer could be continuously casted when the moving speed of the dummy bar was 6 cm/min, but liquid silicon extruded from the growth region without solidification when the moving speed of the dummy bar was ${\geq}$ 9 cm/min. This was due to a shift of the position of the solid-liquid interface from the solidification zone to the moving area. The present study reports experimental findings on a new direct growth system for obtaining silicon wafers with both high quality and productivity, as a candidate for an alternate route for the fabrication of ribbon-type silicon wafers.

• Journal of the Korean institute of surface engineering
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• v.47 no.5
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• pp.227-232
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• 2014

In this study, we propose the application of doping process technology for atmospheric pressure plasma. The plasma treatment means the wafer is warmed via resistance heating from current paths. These paths are induced by the surface charge density in the presence of illuminating Argon atmospheric plasmas. Furthermore, it is investigated on the high-concentration doping to a selective partial region in P type solar cell wafer. It is identified that diffusion of impurities is related to the wafer temperature. For the fixed plasma treatment time, plasma currents were set with 40, 70, 120 mA. For the processing time, IR(Infra-Red) images are analyzed via a camera dependent on the temperature of the P type wafer. Phosphorus concentrations are also analyzed through SIMS profiles from doped wafer. According to the analysis for doping process, as applied plasma currents increase, so the doping depth becomes deeper. As the junction depth is deeper, so the surface resistance is to be lowered. In addition, the surface charge density has a tendency inversely proportional to the initial phosphorus concentration. Overall, when the plasma current increases, then it becomes higher temperatures in wafer. It is shown that the diffusion of the impurity is critically dependent on the temperature of wafers.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.4
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• pp.53-60
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• 2003

CCD(Charge-Coupled Device) wafers, with a layer of micro lenses on top, usually are not passivated with dielectric films. Micro lenses, in general, are made of polymer material, which usually has a large affinity for particles generated in the various chip fabrication processes, most notably the wafer sawing for chip-dicing. The particles deposited on the micro lens layer either seriously attenuate or deflect the incoming light and often lead to CCD failure. In this study we introduce new type of saws which would significantly reduce the particle-related problems found in conventional type of saws. In the new saws, the positions and diverging angles of side and center nozzles have been optimized so as to flush the particles effectively. In addition, an independent nozzle is added for the sole purpose of flushing the generated particles. The test results show that, with the new saws. the ratio of the particle-related CCD chip failures has been dropped drastically from 9.1% to 0.63%.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.11 s.176
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• pp.165-172
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• 2005

In MEMS (Micro-Electro-Mechanical System), packaging induced stress or stress induced structure deformation becomes increasing concerns since it directly affects the performance of the device. In the decoupled vibratory MEMS gyroscope, the main factor that determines the yield rate is the frequency difference between the sensing and driving modes. The gyroscope, packaged using the anodic bonding at the wafer level and EMC (epoxy molding compound) molding, has a deformation of MEMS structure caused by thermal expansion mismatch. This effect results in large distribution in the frequency difference, and thereby a lower yield rate. To improve the yield rate we propose a packaged SiOG (Silicon On Glass) process technology. It uses a silicon wafer and two glass wafers to minimize the wafer warpage. Thus the warpage of the wafer is greatly reduced and the frequency difference is more uniformly distributed. In addition. in order to increase robustness of the structure against deformation caused by EMC molding, a 'crab-leg' type spring is replaced with a semi-folded spring. The results show that the frequency shift is greatly reduced after applying the semi-folded spring. Therefore we can achieve a more robust vibratory MEMS gyroscope with a higher yield rate.

• Proceedings of the Korean Society of Laser Processing Conference
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• 2006.11a
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• pp.128-132
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• 2006

Low-k wafer engraving process has been investigated by using UV pico-second laser with high repetition rate. Wavelength and repetition rate of laser used in this study are 355nm and 80MHz, respectively. Main parameters of low-k wafer engraving processes are laser power, work speed, assist gas flow rate, and protective coating to eliminate debris. Results show that engraving qualities of low-k layer by using UV pico-second pulse width and high repetition rate had better kerf edge and higher work speed, compared to one by conventional laser with nano-second pulse width and low repetition rate in the range of kHz. Assist gas and protective coating to eliminate debris gave effects on the quality of engraving edge. Total engraving width and depth are obtained less than $20{\mu}m$ and $10{\mu}m$ at more than 500mm/sec work speed, respectively. We believe that engraving method by using UV pico-second laser with high repetition rate is useful one to give high work speed of laser material process.

• Korean Journal of Materials Research
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• v.11 no.3
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• pp.159-163
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• 2001

The success of SDB (silicon wafer direct bonding) technology can be estabilished by bonding on the bonded interface with no defects and Preventing temperature dependent bubbles. In this research, we observed the behavior of the intrinsic bubbles by transmitting the infrared light and the increase of the bubble pressure was found. And, the $SiO_2$-$SiO_2$ bonded wafer was achieved, which generates no intrinsic bubbles in the annealing under the atmospheric pressure. The intrinsic bubbles in the $SiO_2$-$SiO_2$ bonded wafer were generated in the annealing in the ultra high vacuum. This experimental result shows the relation between the bubble growth and the pressure.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.261-278
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• 2003

Concepts.Wafer-Level Chip-Scale Concept with Handling Substrate.Low Accuracy Placement Layout with Isolation Trench.Possible Pitch of Interconnections down to $10{\mu}{\textrm}{m}$ (Sn-Grains).Wafer-to-Wafer Equipment Adjustment Accuracy meets this Request of Alignment Accuracy (+/-1.5 ${\mu}{\textrm}{m}$).Adjustment Accuracy of High-Speed Chip-to-Wafer Placement Equipment starts to meet this request.Face-to-Face Modular / SLID with Flipped Device Orientation.interchip Via / SLID with Non-Flipped Orientation SLID Technology Features.Demonstration with Copper / Tin-Alloy (SLID) and W-InterChip Vias (ICV).Combination of reliable processes for advanced concept - Filling of vias with W as standard wafer process sequence.No plug filling on stack level necessary.Simultanious formation of electrical and mechanical connection.No need for underfiller: large area contacts replace underfiller.Cu / Sn SLID layers $\leq$ $10{\mu}{\textrm}{m}$ in total are possible Electrical Results.Measurements of Three Layer Stacks on Daisy Chains with 240 Elements.2.5 Ohms per Chain Element.Contribution of Soldering Metal only in the Range of Milliohms.Soldering Contact Resistance ($0.43\Omega$) dominated by Contact Resistance of Barrier and Seed Layer.Tungsten Pin Contribution in the Range of 1 Ohm

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2002.05a
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• pp.29-30
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• 2002

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.11a
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• pp.75-78
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• 2000

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.811-812
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• 2012