• Title/Summary/Keyword: On-Wafer

Search Result 2,269, Processing Time 0.038 seconds

Effects of Oxide Layer Formed on TiN Coated Silicon Wafer on the Friction and Wear Characteristics in Sliding (미끄럼운동 시 TiN 코팅에 형성되는 산화막이 마찰 및 마멸 특성에 미치는 영향)

  • 조정우;이영제
    • Tribology and Lubricants
    • /
    • v.18 no.4
    • /
    • pp.260-266
    • /
    • 2002
  • In this study, the effects of oxide layer farmed on the wear tracks of TiN coated silicon wafer on friction and wear characteristics were investigated. Silicon wafer was used for the substrate of coated disk specimens, which were prepared by depositing TiN coating with 1 ${\mu}{\textrm}{m}$ in coating thickness. AISI 52100 steel ball was used fur the counterpart. The tests were performed both in air for forming oxide layer on the wear track and in nitrogen to avoid oxidation. This paper reports characterization of the oxide layer effects on friction and wear characteristics using X-ray diffraction(XRD), Auger electron spectroscopy(AES), scanning electron microscopy (SEM) and multi-mode atomic force microscope(AFM).

Effects of oxide layer formed on TiN coated silicon wafer on the friction characteristics

  • Cho, C.W.;Lee, Y.Z.
    • Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
    • /
    • 2002.10b
    • /
    • pp.167-168
    • /
    • 2002
  • In this study, the effects of oxide layer formed on the wear tracks of TiN coated silicon wafer on friction characteristics were investigated. Silicon wafer was used for the substrate of coated disk specimens, which were prepared by depositing TiN coating with $1\;{\mu}m$ in coating thickness. AISI 52100 steel balls were used for the counterpart. The tests were performed both in air for forming oxide layer on the wear track and in nitrogen to avoid oxidation. This paper reports characterization of the oxide layer effects on friction characteristics using X-ray diffraction (XRD). scanning electron microscopy (SEM) and friction force microscope (FFM).

  • PDF

The effect of micro/nano-scale wafer deformation on UV-nanoimprint lithography using an elementwise patterned stamp (다중양각스탬프를 사용하는 UV 나노임프린트 리소그래피공정에서 웨이퍼 미소변형의 영향)

  • 정준호;심영석;최대근;김기돈;신영재;이응숙;손현기;방영매;이상찬
    • Proceedings of the Korean Society of Precision Engineering Conference
    • /
    • 2004.10a
    • /
    • pp.1119-1122
    • /
    • 2004
  • In the UV-NIL process using an elementwise patterned stamp (EPS), which includes channels formed to separate each element with patterns, low-viscosity resin droplets with a nano-liter volume are dispensed on all elements of the EPS. Following pressing of the EPS, the EPS is illuminated with UV light to cure the resin; and then the EPS is separated from several thin patterned elements on a wafer. Experiments on UV-NIL were performed on an EVG620-NIL. 50 - 70 nm features of the EPS were successfully transferred to 4 in. wafers. Especially, the wafer deformation during imprint was analyzed using the finite element method (FEM) in order to study the effect of the wafer deformation on the UV-NIL using EPS.

  • PDF

A study on the Digital contents for Estimated Thickness Algorithm of Silicon wafer (실리콘웨이퍼 평탄도 추정 알고리즘을 위한 디지털 컨덴츠에 관한 연구)

  • Song Eun-Jee
    • Journal of Digital Contents Society
    • /
    • v.5 no.4
    • /
    • pp.251-256
    • /
    • 2004
  • The flatness of a silicon wafer concerned with ULSI chip is one of the most critical parameters ensuring high yield of wafers. That is necessary to constitute the circuit with high quality for he surface of silicon wafer, which comes to be base to make the direct circuit of the semiconductor, Flatness, therefore, is the most important factor to guarantee it wafer with high quality. The process of polishing is one of the most crucial production line among 10 processing stages to change the rough surface into the flatnees with best quality. Currently at this process, it is general for an engineer in charge to observe, judge and control the model of wafer from the monitor of measuring equipment with his/her own eyes to enhance the degree of flatness. This, however, is quite a troublesome job for someone has to check of process by one's physical experience. The purpose of this study is to approach the model of wafer with digital contents and to apply the result of the research for an algorithm which enables to control the polishing process by means of measuring the degree of flatness automatically, not by person, but by system. In addition, this paper shows that this algorithm proposed for the whole wafer flatness enables to draw an estimated algorithm which is for the thickness of sites to measure the degree of flatness for each site of wafer.

  • PDF

Analysis on Bowing and Formation of Al Doped P+ Layer by Changes of Thickness of N-type Wafer and Amount of Al Paste (N타입 결정질 실리콘 웨이퍼 두께 및 알루미늄 페이스트 도포량 변화에 따른 Bowing 및 Al doped p+ layer 형성 분석)

  • Park, Tae Jun;Byun, Jong Min;Kim, Young Do
    • Korean Journal of Materials Research
    • /
    • v.25 no.1
    • /
    • pp.16-20
    • /
    • 2015
  • In this study, in order to improve the efficiency of n-type monocrystalline solar cells with an Alu-cell structure, we investigate the effect of the amount of Al paste in thin n-type monocrystalline wafers with thicknesses of $120{\mu}m$, $130{\mu}m$, $140{\mu}m$. Formation of the Al doped $p^+$ layer and wafer bowing occurred from the formation process of the Al back electrode was analyzed. Changing the amount of Al paste increased the thickness of the Al doped $p^+$ layer, and sheet resistivity decreased; however, wafer bowing increased due to the thermal expansion coefficient between the Al paste and the c-Si wafer. With the application of $5.34mg/cm^2$ of Al paste, wafer bowing in a thickness of $140{\mu}m$ reached a maximum of 2.9 mm and wafer bowing in a thickness of $120{\mu}m$ reached a maximum of 4 mm. The study's results suggest that when considering uniformity and thickness of an Al doped $p^+$ layer, sheet resistivity, and wafer bowing, the appropriate amount of Al paste for formation of the Al back electrode is $4.72mg/cm^2$ in a wafer with a thickness of $120{\mu}m$.

The Characteristics of the Wafer Bonding between InP Wafers and $\textrm{Si}_3\textrm{N}_4$/InP (Direct Wafer Bonding법에 의한 InP 기판과 $\textrm{Si}_3\textrm{N}_4$/InP의 접합특성)

  • Kim, Seon-Un;Sin, Dong-Seok;Lee, Jeong-Yong;Choe, In-Hun
    • Korean Journal of Materials Research
    • /
    • v.8 no.10
    • /
    • pp.890-897
    • /
    • 1998
  • The direct wafer bonding between n-InP(001) wafer and the ${Si}_3N_4$(200 nm) film grown on the InP wafer by PECVD method was investigated. The surface states of InP wafer and ${Si}_3N_4$/InP which strongly depend upon the direct wafer bonding strength between them when they are brought into contact, were characterized by the contact angle measurement technique and atomic force microscopy. When InP wafer was etched by $50{\%}$ HF, contact angle was $5^{\circ}$ and RMS roughness was $1.54{\AA}$. When ${Si}_3N_4$ was etched by ammonia solution, RMS roughness was $3.11{\AA}$. The considerable amount of initial bonding strength between InP wafer and ${Si}_3N_4$/InP was observed when the two wafer was contacted after the etching process by $50{\%}$ HF and ammonia solution respectively. The bonded specimen was heat treated in $H^2$ or $N^2$, ambient at the temperature of $580^{\circ}C$-$680^{\circ}C$ for lhr. The bonding state was confirmed by SAT(Scannig Acoustic Tomography). The bonding strength was measured by shear force measurement of ${Si}_3N_4$/InP to InP wafer increased up to the same level of PECVD interface. The direct wafer bonding interface and ${Si}_3N_4$/InP PECVD interface were chracterized by TEM and AES.

  • PDF

Removal of Post Etch/Ash Residue on an Aluminum Patterned Wafer Using Supercritical CO2 Mixtures with Co-solvents and Surfactants: the Removal of Post Etch/Ash Residue on an Aluminum Patterned Wafer

  • You, Seong-sik
    • Journal of the Semiconductor & Display Technology
    • /
    • v.16 no.2
    • /
    • pp.55-60
    • /
    • 2017
  • The supercritical $CO_2$ (sc-$CO_2$) mixture and the sc-$CO_2$-based Photoresist(PR) stripping(SCPS) process were applied to the removal of the post etch/ash PR residue on aluminum patterned wafers and the results were observed by scanning of electron microscope(SEM). In the case of MDII wafers, the carbonized PR was able to be effectively removed without pre-stripping by oxygen plasma ashing by using sc-$CO_2$ mixture containing the optimum formulated additives at the proper pressure and temperature, and the same result was also able to be obtained in the case of HDII wafer. It was found that the efficiency of SCPS of ion implanted wafer improved as the temperature of SCPS was high, so a very large amount of MEA in the sc-$CO_2$ mixture could be reduced if the temperature could be increased at condition that a process permits, and the ion implanted photoresist(IIP) on the wafer was able to be removed completely without pre-treatment of plasma ashing by using the only 1 step SCPS process. By using SCPS process, PR polymers formed on sidewalls of metal conductive layers such as aluminum films, titanium and titanium nitride films by dry etching and ashing processes were removed effectively with the minimization of the corrosion of the metal conductive layers.

  • PDF

Algorithm and control of aligners (Aligner 알고리즘 및 제어)

  • 박종현
    • 제어로봇시스템학회:학술대회논문집
    • /
    • 1993.10a
    • /
    • pp.981-986
    • /
    • 1993
  • A fast algorithm based upon geometry to measure the wafer center and the position of a wafer fiducial mark is developed and implemented on a single-axis aligner. Design issues for a controller when a National Semiconductor's LM629 is used as a PID controller of an aligner are discussed. Performance of an aligner with the algorithm and a LM629 was measured in experiments. The result shows that it takes about 4.1 seconds on average to align a hot wafer supported by metal pins on the chuck.

  • PDF