• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 Techno-Fair 및 추계학술대회 논문집 전기물성,응용부문
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• pp.148-149
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• 2007

We present the design and fabrication prcoess of a two-axis tilting micromirror device driven by the electrostatic vertical comb actuator. A high aspect-ratio comb actuator is fabricated by multiple DRIE process in order to achieve large scan angle. The proposed fabrication process enables a mirror to be fabricated on the wafer-scale. By bonding a double-side polished (DSP) wafer and a silicon-on-insulator (SOI) wafer together, all actuators on the wafer are completely hidden under the reflectors. Nickel lines are embedded on a Pyrex wafer for the electrical access to numerous electrodes of mirrors. An anodic bonding step is implemented to contact electrical lines with ail electrodes on the wafer at a time. The mechanical angle of a fabricated mirror has been measured to be 1.9 degree and 1.6 degree, respectively, in the two orthogonal axes under driving voltages of 100 V. Also, a $8{\times}8$ array of micromirrors with high fill-factor of 70 % is fabricated by the same fabrication process.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• 한국생산제조학회지
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• 제22권1호
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• pp.168-172
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• 2013

In 3D wafer-stacking technology, one of the major issues is wafer warpage. Especially, The important reason of warpage has been known due to CTE(Coefficient of Thermal Expansion) mismatch between materials. It was too hard to choose how to make the FE model for blanket structured wafer level 3D packaging, because the thickness of each layer in wafer level 3D packaging was too small (micro meter or nano meter scale) comparing with diameter of wafer (6 or 8 inches). In this study, the FE model using the shell element was selected and simulated by the ANSYS WorkBench to investigate effects of the CTE on the warpage. To verify the FE model, it was compared by experimental results.

• 반도체디스플레이기술학회지
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• 제5권2호
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• pp.41-46
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• 2006

Wet etching process in recent semiconductor manufacturing is devided into batch and single wafer type. Batch type wet etching process provides more throughput with poor etching uniformity compared to single wafer type process. Single wafer process achieves better etching uniformity by boom-swing injected chemical on rotating wafer. In this study, etching characteristics of $SiO_2$ layer at room and elevated temperature is evaluated and compared. The difference in etching rate and uniformity of each condition is identified, and the temperature profile of injected chemical is theoretically calculated and compared to that of experimental result. Better etching uniformity is observed with single wafer tool with boom-swing injection compared to single wafer process without boom-swing or batch type tool.

• 대한전자공학회논문지SD
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• 제45권8호
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• pp.11-16
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• 2008

본 논문에서는 먼저 RTP(Rapid Thermal Processor) 장치를 스트레스 측정에 용이한 구조로 제작하고 PC에서 통합 공정관리 시스템을 설계하였다. 다음으로는 Large deformation 이론을 바탕으로 반도체 웨이퍼 표면의 변형검사를 위한 레이져 인터페로미터리를 구성하였다. 궁극적으로 이러한 레이져장치로부터 웨이퍼 표면의 영상을 추출하고 세선화, 블록화 그리고 스트레스 분포도의 순서로 영상처리 하여 스트레스로 인한 웨이퍼 표면의 변형을 검사하였다. 실험을 하기 위해 변형이 이루어지도록 웨이퍼의 후면을 1mm정도 갈아낸 후 약 1000도에서 $3\sim4$회 열처리를 수행하였으며, 열처리를 가한 영상과 가하지 않은 영상을 통하여 웨이퍼 열처리 후 심각한 변형이 이루어졌음을 알 수 있었다.

• 한국멀티미디어학회논문지
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• 제13권3호
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• pp.400-409
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• 2010

본 논문에서는 반도체 생산 공정 중 클리닝 공정 설비에서, 웨이퍼의 장착 위치를 인식하는 영상 인식 시스템을 제안한다. 제안한 시스템은 웨이퍼의 위치 이탈에 따른 위치오차 발생 시 이를 클리닝 설비에 전달하여, 웨이퍼 클리닝 장비의 파손을 방지하여 시스템의 신뢰성과 경제성을 높이기 위한 것이다. 시스템의 주요 알고리즘은 카메라에 획득된 영상과 실제 웨이퍼간의 캘리브레이션 방법, 적외선 조명 및 필터 설계, 최소자승법 기반의 원 생성알고리즘에 의한 중심위치 판별법이다. 제안한 시스템은 고 신뢰성과 고 정밀의 위치인식 알고리즘을 사용하여, 효율적으로 웨이퍼 인라인 공정에 설치함을 목표로 하며 실험결과 충분한 허용 기준 내에서 오차를 검출해내는 좋은 성능을 보여준다.

• 한국재료학회지
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• 제23권6호
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• pp.316-321
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• 2013

The electrical properties and surface morphology changes of a silicon wafer as a function of the HF concentration as the wafer is etched were studied. The HF concentrations were 28, 30, 32, 34, and 36 wt%. The surface morphology changes of the silicon wafer were measured by an SEM ($80^{\circ}$ tilted at ${\times}200$) and the resistivity was measured by assessing the surface resistance using a four-point probe method. The etching rate increased as the HF concentration increased. The maximum etching rate 27.31 ${\mu}m/min$ was achieved at an HF concentration of 36 wt%. A concave wave formed on the wafer after the wet etching process. The size of the wave was largest and the resistivity reached 7.54 $ohm{\cdot}cm$ at an 30 wt% of HF concentration. At an HF concentration of 30 wt%, therefore, a silicon wafer should have good joining strength with a metal backing as well as good electrical properties.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 일렉트렛트 및 응용기술
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• pp.223-227
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• 2002

As the channel length of device shrinks below $0.13{\mu}m$, CMP(chemical mechanical polishing) process got into key process for global planarization in the chip manufacturing process. The removal rate and non-uniformity of the CMP characteristics occupy an important position to CMP process control. Especially, the post-CMP thickness variation depends on the device yield as well as the stability of subsequent process. In this paper, every wafer polished two times for the improvement of oxide CMP process characteristics. Then, we discussed the removal rate and non-uniformity characteristics of post-CMP process. As a result of CMP experiment, we have obtained within-wafer non-uniformity (WIWNU) below 4 [%], and wafer-to-wafer non-uniformity (WTWNU) within 3.5 [%]. It is very good result, because the reliable non-uniformity of CMP process is within 5 [%].

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.555-556
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• 2006

In recent years, the higher flatness level in wafer shape has been strictly demanded with a high integration of the semiconductor devices. It has become difficult for a conventional wafer preparing process to satisfy those demands. In order to meet those demands, surface grinding with in-feed grinder is adopted. In an in-feed grinding method, a chuck table fur fixing a semiconductor wafrr rotates on its rotation axis with a slight tilt angle to the rotation axis of a cup shaped grinding wheel and the grinding wheel in rotation moves down to grind the wafer. So, stability of the grinder structure is very important to aquire a wafer of good quality. This paper describes the features of the in-feed grinder and some FEM analysis results of the grinder structure.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.323-323
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• 2010

Saw damage of crystalline silicon wafer is unavoidable factor. Usually, alkali treatment for removing the damage has been carried out as the saw damage removal (SDR) process for priming the alkali texture. It usually takes lots of time and energy to remove the sawed damages for solar grade crystalline silicon wafers We implemented two different mixed acidic solution treatments to obtain the improved surface structure of silicon wafer without much sacrifice of the silicon wafer thickness. At the first step, the silicon wafer was dipped into the mixed acidic solution of $HF:HNO_3$=1:2 ration for polished surface and at the second step, it was dipped into the diluted mixed acidic solution of $HF:HNO_3:H_2O$=7:3:10 ratio for porous structure. This double treatment to the silicon wafer brought lower reflectance (25% to 6%) and longer carrier lifetime ($0.15\;{\mu}s$ to $0.39\;{\mu}s$) comparing to the bare poly-crystalline silicon wafer. With optimizing the concentration ratio and the dilution ratio, we can not only effectively substitute the time consuming process of SDR to some extent but also skip plasma enhanced chemical vapor deposition (PECVD) process. Moreover, to conduct alkali texture for pyramidal structure on silicon wafer surface, we can use only nitric acid rich solution of the mixed acidic solution treatment instead of implementing SDR.