• EDISON SW 활용 경진대회 논문집
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• 제5회(2016년)
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• pp.183-189
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• 2016

In this paper, an optimization study on a helicopter rotor blade cross-section was made. Generalization was made to the baseline cross-section to simplify the analysis. To have better performance in aeroelastic response, with the aerodynamic center being the origin of the baseline, the distance between aerodynamic center and shear center, and the distance between mass center and shear center of the blade were minimized. For efficient searching of optimum solutions over the design space, grid search method, which is a method of graphical search was used. Two design variables, radius of balancing weight at leading edge, and offset of the spar from leading edge were selected for the study. Cubic spline interpolation method was used to accommodate searching of the optimum solution. 2-Leveled searching system was devised in accordance with the interpolation method. Optimum solution was found to show 6% decrease in both distance between aerodynamic center and shear center, and mass center and shear center to the baseline.

• Journal of Power Electronics
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• 제18권5호
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• 대한기계학회논문집A
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• 제28권7호
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• pp.1038-1046
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• 2004

In order to acquire high-speed and high-precision performances in servomechanisms, an integrated design method have been proposed. Based on strict mathematical modeling and analysis of system performance according to design and operating parameters, a nonlinear constrained optimization problem including the relevant subsystem parameters of the servomechanism is formulated. Optimum design results of mechanical and electrical parameters are obtained according to the design parameters specified by designers through the integrated design processes. Motors are optimally selected from the servo motor database. Both the geometric errors referring to Abbe offset and the contour errors are minimized while required constraints such as stability conditions and saturated conditions are satisfied. This design methodology both offers the improved possibility to evaluate and optimize the dynamic motion performance of the servomechanism and improves the quality of the design process to achieve the required performance for high-speed/precision servomechanisms.

• Journal of Welding and Joining
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• 제33권1호
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• pp.54-60
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• 2015

Laser-arc hybrid welding has been considered as an effective pipe girth welding process since early 2000's. Tolerance for fit-up offsets such as gap and edge misalignment is one of most important requirements in pipe girth laser-arc hybrid welding, and several approaches using parameter optimization, a laser beam scanning and an arc oscillation have been tried. However the required offset tolerance has not been fully accomplished up to now and laser-arc hybrid welding has not been widely applied in pipeline construction than expected, despite of its high welding speed and deep penetration. In this study, internal welding was adopted to ensure the offset tolerance and sound back bead. The effect of welding parameters on bead shape was investigated at the flat position. Also tolerances for gap and edge misalignment were verified as 0.5 mm and 2.0 mm, respectively. The position welding trials were conducted at several welding positions from the flat to the overhead position in a downward direction. With the fixed welding speed, arc current for gas metal arc welding current and laser output power, adequate welding voltages for gas metal arc welding were suggested for each position.

• 한국자동차공학회논문집
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• 제13권2호
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• pp.108-113
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• 2005

The damageability and repairability of similar platform type vehicles could be very concerned with design optimization. In all the vehicles crash tested, small size passenger vehicles were weakness in aspect of damageability and repairability. The most critical area appears to be repair cost considering that parts cost is the largest portion of total repair cost segments. Besides repair cost, attaching method of front sidemember and subframe are placed special importance for impact energy absorption and damageability and repairability. So in order to improve damageability and repairability of vehicle structure and body component of the monocoque type passenger vehicles, the end of front side member and front back beam should be designed with optimum level and to supply the end of front side member as a partial condition approx 300mm. The effectiveness of design concept on the 40% offset frontal impact characteristics of the passenger vehicle structure is investigated and summarized.

• 에너지공학
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• 제24권2호
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• pp.72-78
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• 2015

본 연구에서는 가스 터빈의 효율을 증대시키는데 사용되는 리큐퍼레이터의 성능에 대한 실험적 연구를 수행하였다. 본 연구에서 채택한 리큐퍼레이터는 오프셋 스트립 휜을 가지는 대항류 열교환기이다. 기존에 제시된 상관식 및 이상상태 사이클 해석을 통하여 최적화된 리큐퍼레이터의 형상을 결정하였다. 리큐퍼레이터의 성능을 평가하기 위해 실험연구를 수행하였다. 특히 리큐퍼레이터의 고온부 입구 온도를 변화시키면서 실험을 수행하였다. 또한 실험 결과를 기존에 제시되어 있던 상관식들과 비교를 하였다. 그 결과 압력강하는 실험결과와 상관식이 잘 맞지 않았지만 유용도는 실험결과와 상관식이 잘 일치하는 것을 확인하였다.

• Journal of Advanced Marine Engineering and Technology
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• 제36권4호
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• pp.497-503
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• 2012

본 연구의 목적은 고온, 고압 환경에서 사용되는 열교환기의 전열관에서 발생되는 열팽창에 따른 열응력, 진동과 같은 기계적 특성을 개선시키고, 전열부 체적을 최소화시키는 관점에서 실험계획법을 이용하여 구불구불한 관 형상에 대하여 형상최적화를 수행하였다. S-관 형상에 대하여 부분별 용도를 제시하였고, 형상 최적화를 위해서 형상변수 및 범위를 정한 후, 유한요소해석을 수행하여 형상변수에 따른 구조적 특성을 평가하였고, 요인배치법을 이용하여 형상변수의 주효과를 분석한 후, 반응표면법(Response surface Methodology)을 이용하여 회귀방정식을 구하고, 최적화 툴을 이용하여 최적화를 수행하였다.

• 자동차안전학회지
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• 제7권1호
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• pp.27-32
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• 2015

In order to protect occupant during car crash accident, Regulation and NCAP(New Car assessment Program) have been developed among various countries like U.S.A., Europe, Korea and Australia. Especially NCAP scores affect to sales of vehicles. So vehicle makers are trying to get good score in NCAP. Low leg injuries play an important role in Australia and Euro NCAP and these injuries are related with footrest design. Optimization of footrest design in early stage of vehicle development is necessary to obtain better and robust results of low legs during crash tests. In this paper, DFSS method and finite element model were used to optimize the low leg performance in small RHD vehicles. Compared with the lower leg injury of base model, the lower leg injury of proposed model was slightly improved and robustness was enhanced also.

• 방송공학회논문지
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• 제14권6호
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• pp.749-768
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• 2009

본 논문은 H.264/AVC 화면내 부호화에서 부호화 효율 향상을 위해 율-왜곡 최적화를 이용한 화면내 예측 오프셋 보상 방법을 제안한다. H.264/AVC의 화면내 예측 부호화는 주변 블록의 복원 화소들을 현재 부호화하려는 블록의 예측 블록으로 활용함으로써 공간적 상관성을 제거하고 부호화 효율을 향상시킨다. 제안 방법은 화면내 부호화의 예측 오차를 감소시키기 위해, 율-왜곡 비용 관점에서의 최적 값을 갖는 화면내 예측 오프셋을 기존 화면내 예측 블록에 더하여 예측 블록의 정확도를 높인다. 따라서 예측 오차 신호의 양자화된 변환 계수를 감소시키며 원본 블록과 복원된 블록 간의 왜곡을 감소시켜 화면내 블록의 부호화 성능을 향상시킬 수 있다. 추가적으로, 휘도 성분의 부호화 성능 향상을 위해 화면내 예측 오프셋 보상이 사용되는 화면내 블록의 색차 성분에 JM 11.0에서 화면간 부호화에서 사용되는 계수 임계 처리 방법을 적용한다. 본 논문의 실험에서는 제안하는 방법이 JM 11.0과 비교 실험했을 때 High Profile 환경에서 평균 2.45%의 비트율 감소와 최대 4.41%의 비트율을 감소시킬 수 있음을 보인다.

• 대한전자공학회논문지SD
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• 제45권6호
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• pp.60-67
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• 2008

본 논문에서는 Bluetooth, Zigbee, WLAN 등 2.4GHz 대역 ISM-band 응용 분야를 위한 저 전력 주파수 합성기를 설계하였다. 저 전력 특성을 얻기 위해 전류소모가 큰 VCO, prescaler, ${\Sigma}-{\Delta}$ modulator 등의 전력소모를 최적화하는데 중점을 두고 설계하였다. VCO는 전력소모 측면에서 유리한 NP-core 유형의 구조를 선택하여 위상잡음 특성과 전력소모를 최적화하였으며, prescaler는 정적 전류소모가 거의 없는 동적 회로 기술이 적용된 D-F/F을 사용하여 전력소모를 줄였다. 또한 다수의 로직으로 구성되는 3차 ${\Sigma}-{\Delta}$ modulator는 'mapping circuit'으로 구조를 단순화하여 작은 면적과 저 전력소모 특성을 갖도록 하였다. $0.18{\mu}m$ CMOS 공정으로 IC를 제작하여 성능을 측정한 결과 설계된 주파수 합성기는 1.8V 전원전압에서 7.9mA의 전류를 소모하고, 100kHz offset에서 -96dBc/Hz, 1MHz offset에서 -118dBc/Hz의 위상 잡음 특성을 보였다 또한 spur 잡음 특성은 -70dBc이며, 25MHz step의 주파수 변화에 따른 위상 고정 시간은 약 $15{\mu}s$이다. 설계된 회로의 칩 면적은 pad를 포함하여 $1.16mm^2$이며 pad를 제외한 면적은 $0.64mm^2$이다.