• Title/Summary/Keyword: Offset cancellation

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A Calibration-Free 14b 70MS/s 0.13um CMOS Pipeline A/D Converter with High-Matching 3-D Symmetric Capacitors (높은 정확도의 3차원 대칭 커패시터를 가진 보정기법을 사용하지 않는 14비트 70MS/s 0.13um CMOS 파이프라인 A/D 변환기)

  • Moon, Kyoung-Jun;Lee, Kyung-Hoon;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.12 s.354
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    • pp.55-64
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    • 2006
  • This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

Individual Order Intermodulation Distortion Generator Using Series Feedback of Diode and Its Application (다이오드 직렬 궤환을 이용한 개별 차수 혼변조 발생기 및 응용)

  • Son, Kang-Ho;Kim, Seung-Hwan;Kim, Ell-Kou;Kim, Young;Yoon, Young-Chul
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.10
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    • pp.1096-1103
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    • 2008
  • This paper proposes an individual order predistortion linearizer using intermodulation distortion(IMD) generator for cancellation the third and the fifth IMD of power amplifier. The IMD generator for controlling the third and the fifth IMD consist of common Emitter amplifier and Schottky diode. These signals are generated by series feedback of Schottky diode to obtain the inverse AM/AM and AM/PM characteristics of power amplifier. The individual order predistorters are consisted of individual IMD generator, power splitter and combiner. The test results show that the third and the fifth IMD can be improved by a maximum 13.5 dB and 0.9 dB in case of CW 2-tone signals. Also, the Adjacent Channel Leakage Ratio(ACLR) can be improved 2.3 dB, 2.5 dB at ${\pm}0.885$ MHz, ${\pm}1.23$ MHz offset frequency for CD-MA IS-95 2FA signals.