• 전기학회논문지
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• 제64권7호
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• pp.1005-1011
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• 2015

This paper proposes the DC offset compensation algorithm with fast response to the sensed grid voltage in the single-phase grid connected inverter. If the sensor of the grid voltage has problems, the DC offset of the grid voltage can be generated. This error must be resolved because the DC offset can generate the estimated grid frequency error of the phase-locked loop (PLL). In conventional algorithm to compensate the DC offset, the DC offset is estimated by integrating the synchronous reference frame d-axis voltage during one period of the grid voltage. The conventional algorithm has a drawback that is a slow dynamic response because monitoring the one period of the grid voltage is required. the proposed algorithm has fast dynamic response because the DC offset is consecutively estimated by transforming the d-axis voltage to synchronous reference frame without monitoring one cycle time of the grid voltage. The proposed algorithm is verified from PSIM simulation and the experiment.

• Journal of Electrical Engineering and Technology
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• 제11권6호
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• pp.1707-1713
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• 2016

This paper proposes a dc error compensation algorithm using dq-synchronous coordinate transform digital phase-locked-loop in single-phase grid-connected converters. The dc errors are caused by analog to digital conversion and grid voltage during measurement. If the dc offset error is included in the phase-locked-loop system, it can cause distortion in the grid angle estimation with phase-locked-loop. Accordingly, recent study has dealt with the integral technique using the synchronous reference frame phase-locked-loop method. However, dynamic response is slow because it requires to monitor one period of grid voltage. In this paper, the dc offset error compensation algorithm of the improved response characteristic is proposed by using the synchronous reference frame phase-locked-loop. The simulation and the experimental results are presented to demonstrate the effectiveness of the proposed dc offset error compensation algorithm.

• 한국태양에너지학회 논문집
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• 제37권6호
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• pp.1-12
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• 2017

The DC link of Grid-Connected 3-Phase 3-Level T-type Photovoltaic PCS (PV-PCS) consists of two series connected capacitors for using their neutral voltage. The mismatch between two capacitor characteristics and transient states happened in load change cause the imbalance of neutral voltage. As a result, PV-PCS performance is degraded and the system becomes unstable. In this paper, a mathematical model for analyzing the imbalance of neutral voltage is derived and a compensation method using offset voltage is proposed, where offset voltage adjusts the applying time of P-type and N-type small vectors. The validity of the proposed methods is verified by simulation and experiment.

• Journal of Power Electronics
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• 제15권6호
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• pp.1593-1600
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• 2015

This paper proposes a novel compensation algorithm of current offset error for single-phase linear compressor in home appliances. In a half-bridge inverter, current offset error may cause unbalanced DC-link voltage when the DC-link is comprised of two serially connected capacitors. To compensate the current measurement error, the synchronous reference frame transformation is used for detecting the measurement error. When an offset error occurs in the output current of the half-bridge inverter, the d-axis current has a ripple with frequency equal to the fundamental frequency. With the use of a proportional-resonant controller, the ripple component can be removed, and offset error can be compensated. The proposed compensation method can easily be implemented without much computation and additional hardware circuit. The validity of the proposed algorithm is verified through experimental results.

• ETRI Journal
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• 제29권1호
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• pp.45-49
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• 2007

The poly-Si thin film transistor (TFT) shows large variations in its characteristics due to the grain boundary of poly-crystalline silicon. This results in unacceptably large input offset of low-voltage differential signaling (LVDS) receivers. To cancel the large input offset of poly-Si TFT LVDS receivers, a full-digital offset compensation scheme has been developed and verified to be able to keep the input offset under 15 mV which is sufficiently small for LVDS signal receiving.

• 센서학회지
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• 제7권5호
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• pp.300-305
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• 1998

본 논문에서는 옵셋전압 및 full scale 출력전압, 옵셋전압 및 full scale 출력전압의 온도특성이 보상된 집적화 된 실리콘 압력센서를 설계하였다. 신호처리회로는 옵셋전압 및 full scale 출력전압을 원하는 값으로 조정할 수 있고 옵셋전압의 온도 드리프트를 최소화할 수 있으며 출력전압이 양의 온도계수를 갖도록 하여 압저항계수의 온도계수와 상쇄되도록 설계하였다. 설계한 신호처리회로는 바이폴라 공정 파라미터를 이용하여 SPICE로 시뮬레이션하였다. 옵셋전압 및 full scale 출력전압의 조정을 위하여 온도계수가 서로 다른 이온주입저항을 이용하였다. 시뮬레이션결과 옵셋전압 및 옵셋전압의 온도계수 조정저항을 이용하여 옵셋전압을 0.133V로 조정하였고 온도 드리프트는 $42\;ppm/^{\circ}C$로 감소시킬 수 있었다. full scale 출력전압 조정저항을 이용하여 full scale 출력전압값을 4.65V로 조정하였고 온도보상을 통해 출력전압의 온도계수를 $40\;ppm/^{\circ}C$로 감소시킬 수 있었다.

• 센서학회지
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• 제19권3호
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• pp.230-237
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• 2010

In sensor signal conditioning and processing, offset and drift characteristics of an operational amplifier are an important factor when the amplifier is used for a precise sensor signal amplifier. In order to use it in high accuracy, an expensive trimming or a complex compensation circuit is required. This paper presents the improved sensor signal conditioning and processing device for ubiquitous sensor network(USN) application or general purpose by developing a hardware of the circuit for reducing the offset voltage and drift characteristics, and a software for its control and sensor signal processing. We realize better offset voltage and drift characteristics of the signal conditioning circuit using low cost operational amplifiers. The experimental results show that this technique is effective in improving the performance of the sensor signal processing device.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 추계학술대회
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• pp.848-851
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• 2012

본 논문에서는 듀얼 커패시터를 이용하여 Opamp에서 발생하는 옵셋 전압을 효과적으로 저감 시키는 회로를 소개한다. 제안하는 회로는 기존 Auto-zeroing 방식의 옵셋 전압 저감회로에서 가지는 단점을 보완하기 위해 커패시터와 mos스위치를 추가하였고, Chopping 방식을 응용하여 고주파수에서 효과적으로 옵셋 전압이 저감되도록 설계하였다. 실험은 TSMC 1.8V, $0.18{\mu}m$ 공정을 이용하여 시뮬레이션 및 레이아웃 설계를 하였고, 실험 조건하에 1Ghz의 주파수에서 5mV 이하의 옵셋 전압이 발생되었다. 이를 통해 기존의 Auto-zeroing 옵셋 저감 방식과 비교하여 옵셋 전압이 효과적으로 저감된 것을 확인하였다.

• 한국전자파학회논문지
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• 제27권1호
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• pp.42-49
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• 2016

본 논문에서는 지연 선로의 경로차를 이용하여 4~6 GHz의 연속파 신호를 감지하여 125 MHz의 해상도로 순시 주파수를 측정하는 순시 주파수 측정용 수신기를 설계 및 제작하였다. 수신기는 4 비트 지연 선로 구조를 가졌으며, 전력 분배기, 지연 선로, 전력 합성기, 전력 검파기, 비교기 등으로 구성되었다. 각각의 비트에 배정된 지연 선로의 주파수에 따른 경로 손실 차이를 보상하고, 전력 검파 특성의 주파수 의존성을 보정하기 위해 오프셋 전압 보상을 비교기에 적용하여 측정의 정확성을 향상시켰다.

• ETRI Journal
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• 제34권4호
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• pp.518-526
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• 2012

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.