• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.7
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• pp.1005-1011
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• 2015

This paper proposes the DC offset compensation algorithm with fast response to the sensed grid voltage in the single-phase grid connected inverter. If the sensor of the grid voltage has problems, the DC offset of the grid voltage can be generated. This error must be resolved because the DC offset can generate the estimated grid frequency error of the phase-locked loop (PLL). In conventional algorithm to compensate the DC offset, the DC offset is estimated by integrating the synchronous reference frame d-axis voltage during one period of the grid voltage. The conventional algorithm has a drawback that is a slow dynamic response because monitoring the one period of the grid voltage is required. the proposed algorithm has fast dynamic response because the DC offset is consecutively estimated by transforming the d-axis voltage to synchronous reference frame without monitoring one cycle time of the grid voltage. The proposed algorithm is verified from PSIM simulation and the experiment.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1707-1713
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• 2016

This paper proposes a dc error compensation algorithm using dq-synchronous coordinate transform digital phase-locked-loop in single-phase grid-connected converters. The dc errors are caused by analog to digital conversion and grid voltage during measurement. If the dc offset error is included in the phase-locked-loop system, it can cause distortion in the grid angle estimation with phase-locked-loop. Accordingly, recent study has dealt with the integral technique using the synchronous reference frame phase-locked-loop method. However, dynamic response is slow because it requires to monitor one period of grid voltage. In this paper, the dc offset error compensation algorithm of the improved response characteristic is proposed by using the synchronous reference frame phase-locked-loop. The simulation and the experimental results are presented to demonstrate the effectiveness of the proposed dc offset error compensation algorithm.

• Journal of the Korean Solar Energy Society
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• v.37 no.6
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• pp.1-12
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• 2017

The DC link of Grid-Connected 3-Phase 3-Level T-type Photovoltaic PCS (PV-PCS) consists of two series connected capacitors for using their neutral voltage. The mismatch between two capacitor characteristics and transient states happened in load change cause the imbalance of neutral voltage. As a result, PV-PCS performance is degraded and the system becomes unstable. In this paper, a mathematical model for analyzing the imbalance of neutral voltage is derived and a compensation method using offset voltage is proposed, where offset voltage adjusts the applying time of P-type and N-type small vectors. The validity of the proposed methods is verified by simulation and experiment.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1593-1600
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• 2015

This paper proposes a novel compensation algorithm of current offset error for single-phase linear compressor in home appliances. In a half-bridge inverter, current offset error may cause unbalanced DC-link voltage when the DC-link is comprised of two serially connected capacitors. To compensate the current measurement error, the synchronous reference frame transformation is used for detecting the measurement error. When an offset error occurs in the output current of the half-bridge inverter, the d-axis current has a ripple with frequency equal to the fundamental frequency. With the use of a proportional-resonant controller, the ripple component can be removed, and offset error can be compensated. The proposed compensation method can easily be implemented without much computation and additional hardware circuit. The validity of the proposed algorithm is verified through experimental results.

• ETRI Journal
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• v.29 no.1
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• pp.45-49
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• 2007

The poly-Si thin film transistor (TFT) shows large variations in its characteristics due to the grain boundary of poly-crystalline silicon. This results in unacceptably large input offset of low-voltage differential signaling (LVDS) receivers. To cancel the large input offset of poly-Si TFT LVDS receivers, a full-digital offset compensation scheme has been developed and verified to be able to keep the input offset under 15 mV which is sufficiently small for LVDS signal receiving.

• Journal of Sensor Science and Technology
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• v.7 no.5
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• pp.300-305
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• 1998

In this paper, integrated pressure sensor with calibration of offset voltage and full scale output and temperature compensation of offset voltage and full scale output were designed. The signal conditioning circuitry are designed that calibrate the offset voltage and full scale output to desired values and minimize the temperature drift of offset voltage and full scale output. Designed circuits are simulated using SPICE in a bipolar technology. The ion implanted resistor of different temperature coefficient were used to trimming the desired values. As a results, offset voltage was calibrated to 0.133V and the temperature drift of offset voltage was reduced to $42\;ppm/^{\circ}C$. Also, the full scale output was calibrated to 4.65V and the temperature coefficient of full scale output was reduced to $40ppm/^{\circ}C$ after temperature compensation.

• Journal of Sensor Science and Technology
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• v.19 no.3
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• pp.230-237
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• 2010

In sensor signal conditioning and processing, offset and drift characteristics of an operational amplifier are an important factor when the amplifier is used for a precise sensor signal amplifier. In order to use it in high accuracy, an expensive trimming or a complex compensation circuit is required. This paper presents the improved sensor signal conditioning and processing device for ubiquitous sensor network(USN) application or general purpose by developing a hardware of the circuit for reducing the offset voltage and drift characteristics, and a software for its control and sensor signal processing. We realize better offset voltage and drift characteristics of the signal conditioning circuit using low cost operational amplifiers. The experimental results show that this technique is effective in improving the performance of the sensor signal processing device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.848-851
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• 2012

In this paper, circuit of reducing the offset voltage in Op-amp, effectively, is newly proposed by using dual capacitor. Capacitors and MOS switches are added in proposed circuit to make up for the weak points of previous circuits ofr reducing the offset voltage in auto-zeroing method. Also, it is designed to reduce the offset voltage in high frequency range by using chopping method, effectively. Circuit simulation and layout are executed by TSMC 1.8V, 0.18um process. From the simulation results, it is verified that magnitude of offset voltage is under 5mV and proposed circuit is good for compensation of offset voltage better than previous auto-zeroing method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.1
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• pp.42-49
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• 2016

In this paper, we design and fabricate an instantaneous frequency measurement receiver with a frequency resolution of 125 MHz which detects and measures continuous signals in 4~6 GHz using path difference of delay lines. The receiver has a 4-bit configuration and consists of power dividers, delay lines, power combiners, power detectors, voltage comparator circuits and so on. The accuracy of the instantaneous frequency measurement is improved by applying offset voltage compensation to the comparator circuits to compensate the frequency-dependent path loss of the delay line and the frequency dependence of power detection.

• ETRI Journal
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• v.34 no.4
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• pp.518-526
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• 2012

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.