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A 1.8 V 40-MS/sec 10-bit 0.18-㎛ CMOS Pipelined ADC using a Bootstrapped Switch with Constant Resistance

  • Eo, Ji-Hun;Kim, Sang-Hun;Kim, Mun-Gyu;Jang, Young-Chan
    • Journal of information and communication convergence engineering
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    • v.10 no.1
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    • pp.85-90
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    • 2012
  • A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

A 12b 100 MS/s Three-Step Hybrid Pipeline ADC Based on Time-Interleaved SAR ADCs

  • Park, Jun-Sang;An, Tai-Ji;Cho, Suk-Hee;Kim, Yong-Min;Ahn, Gil-Cho;Roh, Ji-Hyun;Lee, Mun-Kyo;Nah, Sun-Phil;Lee, Seung-Hoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.2
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    • pp.189-197
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    • 2014
  • This work proposes a 12b 100 MS/s $0.11{\mu}m$ CMOS three-step hybrid pipeline ADC for high-speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual-channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a $0.11{\mu}m$ CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of $1.34mm^2$ and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

Design of Ku-Band Phase Locked Harmonic Oscillator (Ku-Band용 위상 고정 고조파 발진기 설계)

  • Lee Kun-Joon;Kim Young-Sik
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.16 no.1 s.92
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    • pp.49-55
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    • 2005
  • In this paper, the phase locked harmonic oscillator(PLHO) using the analog PLL(Phase Locked Loop) is designed and implemented for a wireless LAN system. The harmonic oscillator is consisted of a ring resonator, a varactor diode and a PLL circuit. Because the fundamental fiequency of 8.5 GHz is used as the feedback signal for the PLL and the 2nd harmonic of 17.0 GHz is used as the output, a analog frequency divider for the phase comparison in the PLL system can be omitted. For the simple PLL circuit, the SPD(Sampling Phase Detector) as a phase comparator is used. The output power of the phase locked harmonic oscillator is 2.23 dBm at 17 GHz. The fundamental and 3rd harmonic suppressions are -31.5 dBc and -29.0 dBc, respectively. The measured phase noise characteristics are -87.6 dBc/Hz and -95.4 dBc/Hz at the of offset frequency of 1 kHz and 10 kHz from the carrier, respectively.

Fragmentation Management Method for 6LoWPAN (6LoWPAN에서 단편화 관리 기법)

  • Seo, Hyun-Gon;Han, Jae-Il
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.46 no.5
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    • pp.130-138
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    • 2009
  • 6LoWPAN is IPv6 packets transmission technology at Sensor network over the IEEE 802.15.4 Standard MAC and Physical layer. Adaptation layer between IP layer and MAC layer performs fragmentation and reassembly of packet for transmit IPv6 packets. RFC4944, IETF 6LoWPAN WG standard document define packet fragmentation and reassembly. In this paper, we propose the IRM(Immediate Retransmission Method) and SRM(Selective Retransmission Method) to manage packet fragmentation and reassembly at 6LoWPAN. Each time destination receives a fragmented packet, it sends Ack message to the source node on IRM. However, on SRM, the destination node receives all fragmented packet, it sends Ack message or Nak message to the source node. In this case, Nak message include the dropped packet number. To compare the performance of the proposed schemes, we develop a simulator using C++. The result of simulation shows the proposed schemes provider better performance than RFC4944 standard scheme.

An X-band Oscillator Using a New Hairpin Resonator (새로운 헤어핀 공진기를 이용한 X 밴드 발진기)

  • Seo, Sung-Won;Jeong, Jin-Ho;Park, Chan-Hyeong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.2
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    • pp.250-256
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    • 2008
  • In this paper, an X-band oscillator is presented using a new miniaturized microstrip hairpin resonator. The newly designed hairpin resonator on the microstrip line employs the spiral structure, which shows a higher loaded quality factor and the 50 % reduced circuit area compared to the conventional one at 9.2 GHz. The oscillator using proposed resonator shows the output power of 10.87 dBm, the second harmonic suppression of 41.99 dBc, and the phase noise performance of -101.49 dBc/Hz at 100 kHz offset, which is better than the conventional resonator oscillator by 6.17 dB.

On the Properties and Intersection Feature of the Ductile Shear Zone (Chonju shear zone) near Yongkwang-Eub (영광(靈光) 부근(附近) 연성전단대(延性剪斷帶)(전주전단대(全州剪斷帶))의 성질(性質)과 교차양상(交叉樣相)에 관(關)하여)

  • Jeon, Kyeong Seok;Chang, Tae Woo;Lee, Byung Joo
    • Economic and Environmental Geology
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    • v.24 no.4
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    • pp.435-446
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    • 1991
  • Ductile shear zones developed in Jurassic granites in the Yonggwang area show NE trend at the eastern part and nearly EW trend at the western part, respectively. Judged from shear sense indicators, they have resulted from dextral strike-slip movement. The intersection of both trends is thought to be due to the truncation and offset of NE shear zone Chonju Shear zone by the brittle Yonggwang fault which runs in near EW direction with sinistral movement sense. The simple shear deformation was predominate through the deformation in this ductile shear zone. Based on this deformation mechanism, the shear strain (${\gamma}$) estimated in domain 1 increases from 0.14 at the shear zone margin to 9.41 toward the center of shear zone. Total displacement obtained only from this measured section(JK 59 to JK14) appecars to be 1434.5 meters. The sequential development of microstructures can be divided into three stages; weakly-foliated, well-foliated and banded-foliated stages. In the weakly-foliated stage dislocation glide mechanism might be predominant. In the well-foliated stage grain boundary migration and progressive misorientation of subgrains was remarkable during dynamic recovery and recrystallization. In the banded-foliated stage grain boundary sliding and microfracturing mechanisms accompanied with crushing and cracking were marked. According to strain analysis from quartzites of the metasedimentary rocks, strain intensity (${\gamma}$) of the samples within the ductile shear zone ranges from 2.7 to 5.7, while that of the samples out of the ductile shear zone appears to be about 1.7.

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Study on Design Principle of Reverse Curve in Superhighway (Superhighway 연속곡선의 설계 방침에 대한 연구)

  • Kim, Sungkyu;Kim, Sangyoup;Choi, Jaisung;Min, Dongchan;Jang, Youngsoo;Shin, Joonsoo
    • International Journal of Highway Engineering
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    • v.16 no.6
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    • pp.169-179
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    • 2014
  • PURPOSES : This study is to conduct the research on the design principle for the driver's safety and comfort in installing consecutive curves of superhighway. METHODS : Superhighway does not currently exist in domestic area. Thus, this study is conducted by collecting driving behavior usage of 30 people who are involved in the members of the virtual driving simulation. By identifying the distribution characteristics of each scenario in ANOVA & Tukey Test, the distribution are categorized into three groups. RESULTS : In the case of Group A in Section 3 (R2 entry part), lane departure exceeds the safety standard, which means to be risky condition. And then in the case of Group B and C, the lane departure values applying theoretical formula was evenly distributed compared to the proven values. CONCLUSIONS : Based on the result, the continuous curve design principles at superhighway should follow three standards as follow. First, an additional linear part needs to be inserted between two curves. Second, what if inserting the linear part is difficult, it would be better to insert a curve more than 2,000m. Third, R1/R2 ratio should not be over two. This design primarily aims to the safety of the operator. Such road alignment also meets the expectations of drivers, thus, it may help drivers to be compatible and amenable while driving continuous curve in superhighway.

Design and Verification of IEEE 802.15.4 LR-WPAN 2.4GHz Base-band for Ubiquitous Sensor Network (유비쿼터스 센서 네트워크를 위한 IEEE 802.15.4 LR-WPAN 2.4GHz 베이스 밴드 설계 및 검증)

  • Lee Seung-Yerl;Kim Dong-Sun;Kim Hyun-Sick;Chung Duck-Jin
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.1 s.343
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    • pp.49-56
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    • 2006
  • This paper describes the design and the verification of IEEE 802.15.4 LR-WPAN 2.4GHz Physical layer for Ubiquitous Sensor Network(USN). We designed the Carrier Frequency Offset(CFO) compensation satisfied the frequency tolerance of IEEE 802.15.4 LR-WPAN and the adaptive matched filter that re-setting of the threshold for the symbol synchronization of the various USN environment. The multiplications is reduced 1/16 by this method each other at i, q phases and has 0.5dB performance improvement in detection probability. Proposed baseband system is designed with verilog HDL and implemented using FPGA prototype board.

Design of CMOS LC VCO with Linearized Gain for 5.8GHz/5.2GHz/2.4GHz WLAN Applications (5.8GHz/5.2GHz/2.4GHz 무선 랜 응용을 위한 선형 이득 CMOS LC VCO의 설계)

  • Ahn Tae-Won;Moon Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.6 s.336
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    • pp.59-66
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    • 2005
  • CMOS LC VCO for tri-bind wireless LAN applications was designed in 1.8V 0.18$\mu$m CMOS process. PMOS transistors were chosen for VCO core to reduce flicker noise. The possible operation was verified for 5.8GHz band (5.725$\~$5.825GHz), 5.2GHz band (5.150$\~$5.325GHz), and 2.4GHz band (2.412$\~$2.484GHz) using the switchable L-C resonators. To linearize its frequency-voltage gain (Kvco), optimized multiple MOS varactor biasing technique was used for capacitance linearization and PLL stability improvement. VCO core consumed 2mA current and $570{\mu}m{\times}600{\mu}m$ die area. The phase noise was lower than -110dBc/Hz at 1MHz offset for tri-band frequencies.

Role of Atmospheric Purification by Trees in Urban Ecosystem -in the Case of Yongin- (도시생태계 수목의 대기정화 역할 -용인시를 사례료-)

  • 조현길;안태원
    • Journal of the Korean Institute of Landscape Architecture
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    • v.29 no.3
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    • pp.38-45
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    • 2001
  • This study quantified annual $CO_2$, SO$_2$ and NO$_2$ uptake and annual $O_2$ production by trees in Yongin´s urban ecosystem, and explored values of urban tree plantings in atmospheric purification. Woody plant cover was only 7.7% with planting density of 1. trees/100$m^2$, and the tree-age structure was largely characterized by a young, growing tree population. Annual per capita pollutant emissions from fossil fuel consumption were 7.3t/yr for $CO_2$, 7.6kg/yr for SO$_2$, and 26.6kg/yr for NO$_{x}$. Carbon dioxide storage per unit urban area by trees was 13.1t/ha and the economic value for $CO_2$ storage was ₩6.6millions/ha. Annual atmospheric purification was 2.0t/ha/yr for $CO_2$ uptake, 2.0kg/ha/yr for SO$_2$ uptake, 4.0kg/ha/yr for NO$_2$ uptake and 1.5t/ha/yr for $O_2$ production, and the annual economic value for the atmospheric purification was ₩1.5millions/ha/yr. Urbantrees stored an amount of $CO_2$ equivalent to about 3.1% of the total annual $CO_2$ emissions, and annually offset total $CO_2$ emissions by 0.5%. Annual SO$_2$ and NO$_2$ uptake by trees equaled 0.5% of total SO$_2$ emissions and 0.3% of total NO$_{x}$ emissions, respectively. Urban trees also played an important role through producing annually 9.2 of the $O_2$ requirement for Yongin´s total population, despite relatively poor tree plantings. Future active plantings and greenspace enlargement in the study city could enhance the role of atmospheric purification by urban trees. The results from this study are expected to be useful in emphasizing environment benefits of urban trees, and in urging the continuous necessity for tree planting and management budget.get.

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