• E2M - 전기 전자와 첨단 소재
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• 제4권1호
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• pp.38-44
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• 1991

본 연구는 전기로에 의한 열 산화법에 의해 SiO$_{2}$(88[.angs.])와 ONO(89[.angs.])를 성장시켜 MIS capacitor를 제작한 후, 초 박막 유전체/실리콘 계면에서 전자파 간섭 효과를 실험적으로 비교 검토한 것이다. EWIE현상의 결과로서 첫째. 저 전계영역에 비해 고 전계영역에서 우세하며 둘째. SiO$_{2}$에 비해 ONO가 약하게 나타난다. 그러므로 ONO가 SiO$_{2}$보다 열 전송자 효과에 대한 저항성이 우수함을 알 수 있고 ULSI급의 게이트 절연막으로서의 실용가능성을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.305-309
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• 2002

We have successfully fabricated a Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure using Bi$\sub$4-x/La$\sub$x/Ti$_3$O$\sub$12/ (BLT) ferroelectric thin film and SiO$_2$/Nitride/SiO$_2$ (ONO) stacked buffer layers for single transistor type ferroelectric nonvolatile memory applications. BLT films were deposited on 15 nm-thick ONO buffer layer by sol-gel spin-coating. The dielectric constant and the leakage current density of prepared ONO film were measured to be 5.6 and 1.0 x 10$\^$-8/ A/$\textrm{cm}^2$ at 2MV/cm, respectively, It was interesting to note that the crystallographic orientations of BLT thin films were strongly effected by pre-bake temperatures. X-ray diffraction patterns showed that (117) crystallites were mainly detected in the BLT film if pre-baked below 400$^{\circ}C$. Whereas, for the films pre-baked above 500$^{\circ}C$, the crystallites with preferred c-axis orientation were mainly detected. From the C-V measurement of the MFIS capacitor with c-axis oriented BLT films, the memory window of 0.6 V was obtained at a voltage sweep of ${\pm}$8 V, which evidently reflects the ferroelectric memory effect of a BLT/ONO/Si structure.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.79-82
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• 1998

Film characteristics of thin ONO dielectric layers for MONOS(metal-oxide-nitride-oxide-semiconductor) EEPRM was investigated by AES and AFM. Second derivative spectra of AES Si LVV overlapping peak provided useful information for chemical state analysis of superthin film. The ONO films with dimension of tunneling oxide 24${\AA}$, nitride 33${\AA}$, and blocking oxide 40${\AA}$ were fabricated. During deposition of the LPCVD nitride films on tunneling oxide, this thin oxide was nitrized. When the blocking oxide were deposited on the nitride film, the oxygen not only oxidized the nitride surface, but diffused through the nitride. The results of ONO film analysis exhibits that it is made up of SiO$_2$(blocking oxide)/O-rich SiON(interface/N-rich SiON(nitride)/-rich SiON(interface)/N-rich SiON(nitride)/O-rich SiON(tunneling oxide).

• E2M - 전기 전자와 첨단 소재
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• 제7권2호
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• pp.145-151
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• 1994

The multi-dielectric layer SiOz/Si3N4/SiO2(ONO) is used to scale down the memory device. In this paper, the change of composition in ONO layer due to the process condition and the conduction mechanism are observed. The composition of the oxide film grown through the oxidation of nitride film is analyzed using auger electron spectroscopy(AES). AES results show that oxygen concentration increases at the interface between oxide and nitride layers as the thickness -of the top oxide layer increases. Results of I-V measurement show that the insulating properties improve as the thickness of the top oxide layer increases. But when the thickness of the nitride layer decreases below 63.angs, insulating peoperties of film 28.angs. of top oxide and film 35.angs. turn over showing that insulating property of film 28.angs. of top oxide is better than that of film 35.angs. of top oxide. This phenomenon of turn over is thought as the result of generation of surface state due to oxygen flow into nitride during oxidation process. As the thickness of the top oxide and nitride increases, the electrical breakdown field increases, but when the thickness of top oxide reaches 35.angs, the same phenomenon of turn over occurs. Optimum film thickness for scaled multi-layer dielectric of memory device SONOS is estimated to be 63.angs. of nitride layer and 28.angs. of top oxide layer. In this case, maximum electrical breakdown field and leakage current are 18.5[MV/cm] and $8{\times}{10^-12}$[A], respectively.

• 한국전자통신학회논문지
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• 제16권3호
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• pp.451-456
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• 2021

반도체 메모리 소자의 커패시터에서 셀 커패시턴스의 향상과 scale down을 위해 유전막으로써 적층형 ONO 구조가 도입되었고 이들의 박막화가 지속적으로 시도되고 있으나 공정 처리 과정에서 많은 문제들이 대두되고 있다. 본 연구에서는 L/L LPCVD를 사용하여 약 10Å의 자연산화막 성장을 억제함으로써 3fF/cell의 정전 용량을 확보할 수 있었다. 또한 유전막의 박막화에 따른 질화막의 이상산화에 미치는 영향을 고찰함으로써 내산화성을 확보할 수 있는 유전막 형성의 안정적인 공정 관리 방법을 제안하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.264-264
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• 2011

1T-1C로 구성되는 기존의 dynamic random access memory (DRAM)는 데이터를 저장하기 위해 적절한 커패시턴스를 확보해야 한다. 따라서 커패시터 면적으로 인한 집적도의 한계에 직면해있으며, 이를 대체하기 위한 새로운 DRAM인 1T- DRAM이 연구되고 있다. 기존의 DRAM과 달리 silicon-on-insulator (SOI) 기술을 이용한 1T-DRAM은 데이터 저장을 위한 커패시터가 요구되지 않는다. 정공을 채널의 중성영역에 축적함으로서 발생하는 포텐셜 변화를 이용하며, 이때 발생하는 드레인 전류차를 이용하여 '0'과 '1'을 구분한다. 기존의 완전공핍형 평면구조의 1T-DRAM은 소스 및 드레인 접합부분에서 발생하는 누설전류로 인해 '0' 상태의 메모리 유지특성이 열화되는 단점을 가지고 있다. 따라서 메모리의 보존특성을 향상시키기 위해 소스/드레인 접합영역을 줄여 누설전류를 감소시키는 구조를 갖는 1T-DRAM의 연구가 필요하다. 또한 고유전율을 가지는 Si3N4를 이용한 oxide-nitride-oxide (ONO)구조의 게이트 절연막을 이용하면 동일한 두께에서 더 낮은 equivalent oxide thickness (EOT)를 얻을 수 있기 때문에 보다 저 전압에서 1T-DRAM 동작이 가능하여 기존의 SiO2 단일층을 이용한 1T-DRAM보다 동일 전압에서 더 큰 sensing margin을 확보할 수 있다. 본 연구에서는 누설전류를 감소시키기 위하여 소스 및 드레인이 채널위로 올려진 recessed channel 구조에 ONO 게이트 절연막을 적용한 1T-DRAM을 제작 및 평가하고, 본 구조의 1T-DRAM적용 가능성 및 ONO구조의 게이트 절연막을 이용한 sensing margin 개선을 확인하였다.

• 전자공학회논문지A
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• 제29A권4호
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• pp.28-32
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• 1992

The electrical properties of ONO interpoly dielectrics grown by polycrystalline silicon have been studied. The polysilicon layer deposited as amorphous state kept its surface smoothness even after subsequent heat cycle induced crystallization. Polysilicon was doped with a POCl$_3$ and arsenic ion implantation. Arsenic was implanted in several different doses. The effective barrier heights calculated from F-N plotting method and breakdown fields increased as the polysilicon doping concentration increased. On the other hand they mere degraded when arsenic concentration in polysilicon exceeded 2{\times}10^{20}[cm^{-3}]$. The reliability of dielectric as monitored by TDDB infant fail and breakdown field showed increasing degradation as doping concentration increased

• Transactions on Electrical and Electronic Materials
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• 제16권4호
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• pp.187-189
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• 2015

A charge-trap flash (CTF) thin film transistor (TFT) memory is proposed at a low-temperature process (≤ 450℃). The memory cell consists of a sputtered oxide-nitride-oxide (ONO) gate dielectric and Schottky barrier (SB) source/drain (S/D) junctions using nickel silicide. These components enable the ultra-low-temperature process to be successfully achieved with the ONO gate stacks that have a substrate temperature of room temperature and S/D junctions that have an annealing temperature of 200℃. The silicidation process was optimized by measuring the electrical characteristics of the Ni-silicided Schottky diodes. As a result, the Ion/Ioff current ratio is about 1.4×10⁵ and the subthreshold swing and field effect mobility are 0.42 V/dec and 14 cm²/V·s at a drain voltage of −1 V, respectively.

• E2M - 전기 전자와 첨단 소재
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• 제7권3호
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• pp.231-235
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• 1994

The multi-dielectric layer $SiO_2$/$Si_3{N_4}$/$SiO_2$ (ONO) is used to improve charge retention and to scale down the memory device. The nitride layer of MNOS device is oxidize to form ONO system. During the oxidation of the nitride layer, the change of thickness of nitride layer and generation of interface state between nitride layer and top oxide layer occur. In this paper, effects of oxidation of the nitride layer is studied. The decreases of the nitride layer due to oxidation and trapping characteristics of interface state of multi layer dielectric film are investigated through the C-V measurement and F-N tunneling injection experiment using SONOS capacitor structure. Based on the experimental results, carrier trapping model for maximum flatband voltage shift of multi layer dielectric film is proposed and compared with experimental data. As a results of curve fitting, interface trap density between the top oxide and layer is determined as being $5{\times}10^11$~$2{\times}10^12$[$eV^1$$cm^2$].

• E2M - 전기 전자와 첨단 소재
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• 제9권5호
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• pp.476-482
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• 1996

The multi-dielectric layer SiO$_{2}$/Si$_{3}$N$_{4}$/SiO$_{2}$(ONO) is used to improve electrical capacitance and to scale down the memory device. In this paper, improvement of the capacitance by reducing the bottom oxide thickness in the nitride deposition with load lock(L/L) vacuum system is studied. Bottom oxide thickness under the nitride layer is measured by ellipsometer both in L/L and non-L/L systems. Both results are in the range of 3-10.angs. and 10-15.angs., respectively, independent of the nitride and top oxide thickness. Effective thickness and cell capacitance for SONOS capacitor are in the range of 50-52.angs. and 35-37fF respectively in the case of nitride 70.angs. in L/L vacuum system. Compared with non-L/L system, the bottom oxide thickness in the case of L/L system decreases while cell capacitance increases about 4 fF. The results obtained in this study are also applicable to ONO scaling in the thin bottom oxide region of memory stacked capacitor.