• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.762-763
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• 2016

In realizing a homomorphic encryption system, the operations of encrypt, decypt, and recrypt constitute major portions. The most important common operation for each back-bone operations include a polynomial modulo multiplication for over million-bit integers, which can be obtained by performing integer Fourier transform, also known as number theoretic transform. In this paper, we adopt and modify an algorithm for calculating big integer multiplications introduced by Schonhage-Strassen to propose an efficient algorithm which can save memory. The proposed architecture of number theoretic transform has been implemented on an FPGA and evaluated.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.8
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• pp.2816-2830
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• 2022

Number Theoretic Transform (NTT) is a method to design efficient multiplier for large integer multiplication, which is widely used in cryptography and scientific computation. On top of that, it has also received wide attention from the research community to design efficient hardware architecture for large size RSA, fully homomorphic encryption, and lattice-based cryptography. Existing NTT hardware architecture reported in the literature are mainly designed based on radix-2 NTT, due to its small area consumption. However, NTT with larger radix (e.g., radix-4) may achieve faster speed performance in the expense of larger hardware resources. In this paper, we present the performance evaluation on NTT architecture in terms of hardware resource consumption and the latency, based on the proposed radix-2 and radix-4 technique. Our experimental results show that the 16-point radix-4 architecture is 2× faster than radix-2 architecture in expense of approximately 4× additional hardware. The proposed architecture can be extended to support the large integer multiplication in cryptography applications (e.g., RSA). The experimental results show that the proposed 3072-bit multiplier outperformed the best 3k-multiplier from Chen et al. [16] by 3.06%, but it also costs about 40% more LUTs and 77.8% more DSPs resources.

• Journal of IKEEE
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• v.25 no.1
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• pp.88-94
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• 2021

Public-key cryptographic algorithms such as RSA and ECC, which are currently in use, have used mathematical problems that would take a long time to calculate with current computers for encryption. But those algorithms can be easily broken by the Shor algorithm using the quantum computer. Lattice-based cryptography is proposed as new public-key encryption for the post-quantum era. This cryptographic algorithm is performed in the Polynomial Ring, and polynomial multiplication requires the most processing time. Therefore, a hardware model module is needed to calculate polynomial multiplication faster. Number Theoretic Transform, which called NTT, is the FFT performed in the finite field. The logic verification was performed using HDL, and the proposed design at the transistor level using Hspice was compared and analyzed to see how much improvement in delay time and power consumption was achieved. In the proposed design, the average delay was improved by 30% and the power consumption was reduced by more than 8%.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.12
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• pp.6260-6276
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• 2019

With the rapid development of cloud computing, it raises real questions on privacy protection, which greatly limits the use of cloud computing. However, fully homomorphic encryption (FHE) can make cloud computing consistent with privacy. In this paper, we propose a simpler FHE scheme based on ring LWE problem, with a smaller size of ciphertext and a lower noise-expansion factor for homomorphic multiplication. Then based on our optimized RLWE-based FHE scheme, we propose a fast single-database private information retrieval protocol, combining with batching and number theoretic transform technology.

• The Journal of the Acoustical Society of Korea
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• v.7 no.4
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• pp.31-53
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• 1988

In this work we study extensively the structures and performance characteristics of the block least mean-square (BLMS) adaptive digital filters (ADF's) that can be realized efficiently using the fast Fourier transform (FFT). The weights of a BLMS ADF realized using the FFT can be adjusted either in the time domain or in the frequency domain, leading to the time-domain BLMS(TBLMS) algorithm or the frequency-domain BLMS (FBLMS) algorithm, respectively. In Part Ⅰof the paper, we first present new results on the overlap-add realization and the number-theoretic transform realization of the FBLMS ADF's. Then, we study how we can incorporate the concept of different frequency-weighting on the error signals and the self-orthogonalization of weight adjustment in the FBLMS ADF's , and also in the TBLMS ADF's. As a result, we show that the TBLMS ADF can also be made to have the same fast convergence speed as that of the self-orthogonalizing FBLMS ADF. Next, based on the properties of the sectioning operations in weight adjustment, we discuss unconstrained FBLMS algorithms that can reduce two FFT operations both for the overlap-save and overlap-add realizations. Finally, we investigate by computer simulation the effects of different parameter values and different algorithms on the convergence behaviors of the FBLMS and TBLMS ADF's. In Part Ⅱ of the paper, we will analyze the convergence characteristics of the TBLMS and FBLMS ADF's.