• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.162-162
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• 2010

InSb has received great attentions as a promising candidate for the active layer of infrared photodetectors due to the well matched band gap for the detection of $3{\sim}5\;{\mu}m$ infrared (IR) wavelength and high electron mobility (106 cm2/Vs at 77 K). In the fabrication of InSb photodetectors, passivation step to suppress dark currents is the key process and intensive studies were conducted to deposit the high quality passivation layers on InSb. Silicon dioxide (SiO2), silicon nitride (Si3N4) and anodic oxide have been investigated as passivation layers and SiO2 is generally used in recent InSb detector fabrication technology due to its better interface properties than other candidates. However, even in SiO2, indium oxide and antimony oxide formation at SiO2/InSb interface has been a critical problem and these oxides prevent the further improvement of interface properties. Also, the mechanisms for the formation of interface phases are still not fully understood. In this study, we report the quantitative analysis of indium and antimony oxide formation at SiO2/InSb interface during plasma enhanced chemical vapor deposition at various growth temperatures and subsequent heat treatments. 30 nm-thick SiO2 layers were deposited on InSb at 120, 160, 200, 240 and $300^{\circ}C$, and analyzed by X-ray photoelectron spectroscopy (XPS). With increasing deposition temperature, contents of indium and antimony oxides were also increased due to the enhanced diffusion. In addition, the sample deposited at $120^{\circ}C$ was annealed at $300^{\circ}C$ for 10 and 30 min and the contents of interfacial oxides were analyzed. Compared to as-grown samples, annealed sample showed lower contents of antimony oxide. This result implies that reduction process of antimony oxide to elemental antimony occurred at the interface more actively than as-grown samples.

• 한국세라믹학회지
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• 제43권8호
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• pp.472-478
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• 2006

The effect of compositional and processing variables on a nitriding reaction of silicon powder compact and subsequent post sintering of RBSN (Reaction-Bonded Silicon Nitride) was investigated. The addition of a nitriding agent enhanced nitridation rate substantially at low temperatures, while the formation of a liquid phase between the nitriding agent and the sintering additives at a high temperature caused a negative catalyst effect resulting in a decreased nitridation rate. A liquid phase formed by solely an additive, however, was found to have no effect on nitridation for the additive amount used in this research. The original site of a decomposing pore former was loosely filled by a reaction product ($Si_3N_4$), which provided a specimen with nitriding gas passage. For SRBSN (Sintered RBSN) specimens of high porosity, only a marginal dimensional change was measured after post sintering. Its engineering implication for near-net shaping ability is discussed.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.180-180
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• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• 공업화학
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• 제24권1호
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• pp.31-37
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• 2013

텍스쳐링에 의해 실리콘 웨이퍼의 표면반사율을 감소시키는 것은 실리콘 태양전지의 효율향상을 위해 매우 중요한 공정이다. 본 연구에서는 에칭속도 제어를 위해 촉매제를 포함한 산 용액으로 텍스쳐링 처리한 웨이퍼의 표면효과와 그 태양전지 특성을 평가 고찰하였다. 텍스쳐링 전 $HNO_3-H_2O_2-H_2O$ 용액의 전처리는 표면반사율의 초기 저감효과를 가져왔다. 이는 산화특성에 의해 유기 불순물이 제거되고 텍스쳐링을 위한 핵의 생성에 기인한다고 할 수 있다. 이후 공정에서 불산/질산 용액에 인산 및 초산과 같은 완충제를 첨가한 혼합용액을 제조하고, 적정 농도 조합과 그 처리시간의 최적화를 통해 개선된 텍스쳐링 효과를 얻을 수 있었으며 이 효과는 표면반사율 감소를 통해 확인할 수 있었다. 이렇게 제조된 실리콘 웨이퍼에 반사방지막 코팅 후 태양전지를 제작하여 그 변환효율을 측정한 결과 16.4%의 양호한 특성을 나타냈다. 이는 개선된 텍스쳐링 처리에 의해 저감된 표면특성에 의한 단락전류의 증가에 기인한 것으로 추정된다.

• 한국재료학회지
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• 제10권10호
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• pp.703-708
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• 2000

최근에 상용차용 디젤 엔진의 성능 향상을 목적으로 엔진 설계가 급격히 변화되면서 캠 팔로우어(cam follower)와 캠(cam) 사이에 작용하는 접동면 하중의 증가로 접동면에서의 마모가 중요한 문제가 되고 있다. 본 연구에서는 기존의 주절체 및 소결합금 캠 팔로우어에 비해 내마모성이 우수한 세라믹 캠 팔로우어를 개발하였다. 잔류 응력을 완화시켜주는 중간층을 사용하지 않고 질화규소($Si_3N_4$) 팁과 중탄소강을 활성납재를 사용하여 직접 접합후 냉각시키는 과정에서 두 모재의 열팽창계수차에 의한 크라우닝(crowning, R) 이 형성되도록 하였다. 접합에 사용한 중탄소강은 열팽창시 이력(hysteresis) 거동을 나타내었으며, $A_{c1}$ 변태점인 $723^{\circ}C$ 이하에서 접합할 경우 원하는 크라우닝이 형성되었다. 접합온도가 $723^{\circ}C$ 이상이 되면 크라우닝 (R) 값이 온도에 따라 지수함수적으로 증가하였으며 이는 중탄소강의 상변태에 의한 열팽창.수축의 이력 특성으로 설명되어질 수 있었다. 규격에 맞는 크라우닝이 형성되는 최적 접합 온도는 $700~720^{\circ}C$의 범위였다. 질화규소와 중탄소강의 직접 접합방법으로 접합과 동시에 크라우닝을 형성시키고 제어함으로써 난가공재인 세라믹을 곡면 가공하지 않고도 적당한 곡률을 갖는 저가의 세라믹 캠 팔로우어를 제조할 수 있었다.

• 센서학회지
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• 제9권2호
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• pp.113-119
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• 2000

정류수 내 수소 가스를 감지할 수 있는 Pd 박막을 가진 Pd/Pt 게이트 MISFET 수소센서를 제조하였다. 감지게이트 MISFET와 기준 게이트 MISFET의 차동형 센서로 제작하여 MOSFET 고유의 드리프트를 최소화하였다. 수소유입으로 인한 드리프트는 $Si_3N_4/SiO_2$의 이중 게이트 절연막으로 줄였고, 수소에 의한 Pd의 격자 팽창에 의해 생기는 블리스터는 Pt을 넣어서 제거하였다. Pd 박막을 수소 여과기로 사용한 Pd/Pt 게이트 MISFET 센서로 측정한 결과 $0{\sim}500\;ppm$ 사이에서 선형적인 출력 특성을 얻을 수 있었다. 30 일간 $50^{\circ}C$의 정류수 속에서 장기안정도를 측정하였다. 전체적으로 감지 FET의 게이트 전압은 35 mV 상승하였고, 기준 FET는 48 mV 상승하여 안정한 특성을 나타내었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.377-377
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• 2012

Microprocessor technology now relies on copper for most of its electrical interconnections. Because of the high diffusivity of copper, Atomic layer deposition (ALD) $TaN_x$ is used as a diffusion barrier to prevent copper diffusion into the Si or $SiO_2$. Another problem with copper is that it has weak adhesion to most materials. Strong adhesion to copper is an essential characteristic for the new barrier layer because copper films prepared by electroplating peel off easily in the damascene process. Thus adhesion-enhancing layer of cobalt is placed between the $TaN_x$ and the copper. Because, cobalt has strong adhesion to the copper layer and possible seedless electro-plating of copper. Until now, metal film has generally been deposited by physical vapor deposition. However, one draw-back of this method is poor step coverage in applications of ultralarge-scale integration metallization technology. Metal organic chemical vapor deposition (MOCVD) is a good approach to address this problem. In addition, the MOCVD method has several advantages, such as conformal coverage, uniform deposition over large substrate areas and less substrate damage. For this reasons, cobalt films have been studied using MOCVD and various metal-organic precursors. In this study, we used $C_{12}H_{10}O_6(Co)_2$ (dicobalt hexacarbonyl tert-butylacetylene, CCTBA) as a cobalt precursor because of its high vapor pressure and volatility, a liquid state and its excellent thermal stability under normal conditions. Furthermore, the cobalt film was also deposited at various $H_2/NH_3$ gas ratio(1, 1:1,2,6,8) producing pure cobalt thin films with excellent conformality. Compared to MOCVD cobalt using $H_2$ gas as a reactant, the cobalt thin film deposited by MOCVD using $H_2$ with $NH_3$ showed a low roughness, a low resistivity, and a low carbon impurity. It was found that Co/$TaN_x$ film can achieve a low resistivity of $90{\mu}{\Omega}-cm$, a low root-mean-square roughness of 0.97 nm at a growth temperature of $150^{\circ}C$ and a low carbon impurity of 4~6% carbon concentration.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2011년도 추계학술발표대회 논문집
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• pp.245-248
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• 2011

Many researches have been carried out to improve light absorption in the crystalline silicon solar cell fabrication. The rear reflection is applied to increase the path length of light, resulting in the light absorption enhancement and thus the efficiency improvement mainly due to increase in short circuit current. In this paper, we manufactured the silicon solar cell using the mono crystalline silicon wafers with $156{\times}156mm^2$, 0.5~3.0 ${\Omega}{\cdot}cm$ of resistivity and p-type. After saw damage removal, the dielectric film ($SiN_x$)on the back surface was deposited, followed by surface texturing in the KOH solution. It resulted in single-side texturing wafer. Then the dielectric film was removed in the HF solution. The silicon wafers were doped with phosphorus by $POCl_3$ with the sheet resistance 50 ${\Omega}/{\Box}$ and then the silicon nitride was deposited on the front surface by the PECVD with 80nm thickness. The electrodes were formed by screen-printing with Ag and Al paste for front and back surface, respectively. The reflectance and transmittance for the single-sided and double-sided textured wafers were compared. The double-sided textured wafer showed higher reflectance and lower transmittance at the long wavelength region, compared to single-sided. The completed crystalline silicon solar cells with different back surface texture showed the conversion efficiency of 17.4% for the single sided and 17.3% for the double sided. The efficiency improvement with single-sided textured solar cell resulted from reflectance increase on back surface and light absorption enhancement.

• 한국전기전자재료학회논문지
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• 제33권6호
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• pp.445-449
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• 2020

Non-volatile memory is approaching its fundamental limits with the Si₃N₄ storage layer, necessitating the use of alternative materials to achieve a higher programming/erasing speed, larger storage window, and better data retention at lower operating voltage. This limitation has restricted the development of the charge-trap memory, but can be addressed by using high-k dielectrics. The paper reviews the doping of nitrogen, titanium, and yttrium on high-k dielectrics as a storage layer by comparing MONOS devices with different storage layers. The results show that nitrogen doping increases the storage window of the Gd₂O₃ storage layer and improves its charge retention. Titanium doping can increase the charge capture rate of HfO₂ storage layer. Yttrium doping increases the storage window of the BaTiO₃ storage layer and improves its fatigue characteristics. Parameters such as the dielectric constant, leakage current, and speed of the memory device can be controlled by maintaining a suitable amount of external impurities in the device.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.239-240
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• 2008

As semiconductor devices are scaled down for better performance and more functionality, the Cu-based interconnects suffer from the increase of the resistivity of the Cu wires. The resistivity increase, which is attributed to the electron scattering from grain boundaries and interfaces, needs to be addressed in order to further scale down semiconductor devices [1]. The increase in the resistivity of the interconnect can be alleviated by increasing the grain size of electroplating (EP)-Cu or by modifying the Cu surface [1]. Another possible solution is to maximize the portion of the EP-Cu volume in the vias or damascene structures with the conformal diffusion barrier and seed layer by optimizing their deposition processes during Cu interconnect fabrication, which are currently ionized physical vapor deposition (IPVD)-based Ta/TaN bilayer and IPVD-Cu, respectively. The use of in-situ etching, during IPVD of the barrier or the seed layer, has been effective in enlarging the trench volume where the Cu is filled, resulting in improved reliability and performance of the Cu-based interconnect. However, the application of IPVD technology is expected to be limited eventually because of poor sidewall step coverage and the narrow top part of the damascene structures. Recently, Ru has been suggested as a diffusion barrier that is compatible with the direct plating of Cu [2-3]. A single-layer diffusion barrier for the direct plating of Cu is desirable to optimize the resistance of the Cu interconnects because it eliminates the Cu-seed layer. However, previous studies have shown that the Ru by itself is not a suitable diffusion barrier for Cu metallization [4-6]. Thus, the diffusion barrier performance of the Ru film should be improved in order for it to be successfully incorporated as a seed layer/barrier layer for the direct plating of Cu. The improvement of its barrier performance, by modifying the Ru microstructure from columnar to amorphous (by incorporating the N into Ru during PVD), has been previously reported [7]. Another approach for improving the barrier performance of the Ru film is to use Ru as a just seed layer and combine it with superior materials to function as a diffusion barrier against the Cu. A RulTaN bilayer prepared by PVD has recently been suggested as a seed layer/diffusion barrier for Cu. This bilayer was stable between the Cu and Si after annealing at $700^{\circ}C$ for I min [8]. Although these reports dealt with the possible applications of Ru for Cu metallization, cases where the Ru film was prepared by atomic layer deposition (ALD) have not been identified. These are important because of ALD's excellent conformality. In this study, a bilayer diffusion barrier of Ru/TaCN prepared by ALD was investigated. As the addition of the third element into the transition metal nitride disrupts the crystal lattice and leads to the formation of a stable ternary amorphous material, as indicated by Nicolet [9], ALD-TaCN is expected to improve the diffusion barrier performance of the ALD-Ru against Cu. Ru was deposited by a sequential supply of bis(ethylcyclopentadienyl)ruthenium [Ru$(EtCp)_2$] and $NH_3$plasma and TaCN by a sequential supply of $(NEt_2)_3Ta=Nbu^t$ (tert-butylimido-trisdiethylamido-tantalum, TBTDET) and $H_2$ plasma. Sheet resistance measurements, X-ray diffractometry (XRD), and Auger electron spectroscopy (AES) analysis showed that the bilayer diffusion barriers of ALD-Ru (12 nm)/ALD-TaCN (2 nm) and ALD-Ru (4nm)/ALD-TaCN (2 nm) prevented the Cu diffusion up to annealing temperatures of 600 and $550^{\circ}C$ for 30 min, respectively. This is found to be due to the excellent diffusion barrier performance of the ALD-TaCN film against the Cu, due to it having an amorphous structure. A 5-nm-thick ALD-TaCN film was even stable up to annealing at $650^{\circ}C$ between Cu and Si. Transmission electron microscopy (TEM) investigation combined with energy dispersive spectroscopy (EDS) analysis revealed that the ALD-Ru/ALD-TaCN diffusion barrier failed by the Cu diffusion through the bilayer into the Si substrate. This is due to the ALD-TaCN interlayer preventing the interfacial reaction between the Ru and Si.