• Proceedings of the Optical Society of Korea Conference
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• 2005.07a
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• pp.204-205
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• 2005

Studies on display has been requested some major changes due to the high growth of the handheld terminal market. Therefore, the self emitting OLED(Organic Light Emitting Diode) has been interested as a next generation flat plane display because of its preeminent characteristics such as quick response characteristics, higher performance viewing angle, low power consumption, and panel floating. However, a trend of the display market is moving to three dimensional image processing instead of two dimensional flat display and various researches on display using hologram makes up for the difficulty in three dimensional display using typical flat display. In this study the Lenticular Screen Printing method is presented so that it can be applicable to organic semiconductor display devices and makes possible three dimensional display using flat display for complement the drawback of inorganic semiconductor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.59-66
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• 2000

As multimedia applications become popular, computers increasingly require high-speed DSP for 3-DIM computer graphic. In this Paper, a Macro-cell Library of conditional select adder/subtracter is proposed for DSP within high speed and low power consumption. Using, this design method, we are able to obtain an auto generation of the adder or(and) subtracter from 8-bit to 64-bit. The proposed adder/subtracter has been fabricated with a 0.25${\mu}m$, single-poly, five-metal, N-well CMOS technology. From the experimental results, delay time is 3.43ns, and the power consumption is 42.8${\mu}w$/MHz at the input frequency of 50MHz, at 2.5V single power supply, in case of the 32-bit adder/subtracter.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.9
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• pp.693-696
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• 2011

Recently, amorphous oxide semiconductors (AOSs) based thin-film transistors (TFTs) have received considerable attention for application in the next generation displays industry. The research trends of AOSs based TFTs investigation have focused on the high device performance. The electrical properties of the TFTs are influenced by trap density. In particular, the threshold voltage ($V_{th}$) and subthreshold swing (SS) essentially depend on the semiconductor/gate-insulator interface trap. In this article, we investigated the effects of Ar plasma-treated $SiO_2$ insulator on the interfacial property and the device performances of amorphous indium gallium zinc oxide (a-IGZO) TFTs. We report on the improvement in interfacial characteristics between a-IGZO channel layer and gate insulator depending on Ar power in plasma process, since the change of treatment power could result in different plasma damage on the interface.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.4
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• pp.400-406
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• 2024

Next-generation wide-bandgap semiconductors such as SiC, GaN, and Ga2O3 are being considered as potential replacements for current silicon-based power devices due to their high mobility, larger size, and production of high-quality wafers at a moderate cost. In this study, we investigate the gradual modulation of chemical composition in multi-stacked metal oxide semiconductor thin films to enhance the performance and bias stability of thin-film transistors (TFTs). It demonstrates that adjusting the Ga ratio in the indium gallium oxide (IGO) semiconductor allows for precise control over the threshold voltage and enhances device stability. Moreover, employing multiple deposition techniques addresses the inherent limitations of solution-processed amorphous oxide semiconductor TFTs by mitigating porosity induced by solvent evaporation. It is anticipated that solution-processed indium gallium oxide (IGO) semiconductors, with a Ga ratio exceeding 50%, can be utilized in the production of oxide semiconductors with wide band gaps. These materials hold promise for power electronic applications necessitating high voltage and current capabilities.

• Journal of the Semiconductor & Display Technology
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• v.21 no.1
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• pp.95-102
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• 2022

Since the organic light-emitting diodes (OLEDs) have been widely investigated as next-generation displays, it has been successfully commercialized as a flexible and rollable display. However, there is still wide room and demand to improve the device characteristics such as power efficiency and lifetime. To solve this issue, there has been a wide research effort, and among them, the internal and the external light extraction techniques have been attracted in this research field by its fascinating characteristic of material independence. In this study, a micro-nano composite structured external light extraction layer was demonstrated. A reactive ion etching (RIE) process was performed on the surfaces of hexagonally packed hemisphere micro-lens array (MLA) and randomly distributed sphere diffusing films to form micro-nano composite structures. Random nanostructures of different sizes were fabricated by controlling the processing time of the O₂ / CHF₃ plasma. The fabricated device using a micro-nano composite external light extraction layer showed 1.38X improved external quantum efficiency compared to the reference device. The results prove that the external light extraction efficiency is improved by applying the micro-nano composite structure on conventional MLA fabricated through a simple process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.473-482
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• 2017

Hand gesture recognition is regarded as new Human Computer Interaction (HCI) technologies for the next generation of mobile devices. Previous hand gesture implementation requires a large memory and computation power for hand segmentation, which fails to give real-time interaction with mobile devices to users. Therefore, in this paper, we presents a low latency and memory-efficient hand segmentation architecture for natural hand gesture recognition. To obtain both high memory-efficiency and low latency, we propose a streaming hand contour tracing unit and a fast contour filling unit. As a result, it achieves 7.14 ms latency with only 34.8 KB on-chip memory, which are 1.65 times less latency and 1.68 times less on-chip memory, respectively, compare to the best-in-class.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.9
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• pp.1351-1358
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• 2017

In this work, we investigated radiation hardness of GaN-based transistors which are strong candidates for next-generation power electronics. Field effect transistors with three types of gate structures including metal Schottky gate, recessed gate, and p-AlGaN layer gate were fabricated on AlGaN/GaN heterostructure on Si substrate. The devices were irradiated with energetic protons and alpha-particles. The irradiated transistors exhibited the reduction of on-current and the shift of threshold voltage which were attributed to displacement damage by incident energetic particles at high fluence. However, FET operation was still maintained and leakage characteristics were not degraded, suggesting that GaN-based FETs possess high potential for radiation-hardened electronics.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1497-1502
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• 2013

Recently, the junctionless (JL) transistors realized by a single-type doping process have attracted attention instead of the conventional metal-oxide-semiconductor field-effect transistors (MOSFET). The JL transistor can overcome MOSFET's problems such as the thermal budget and short-channel effect. Thus, the JL transistor is considered as great alternative device for a next generation low standby power silicon system. In this paper, the JL FinFET was simulated with a three dimensional (3D) technology computer-aided design (TCAD) simulator and optimized for DC characteristics according to device dimension and doping concentration. The design variables were the fin width ($W_{fin}$), fin height ($H_{fin}$), and doping concentration ($D_{ch}$). After the optimization of DC characteristics, RF characteristics of JL FinFET were also extracted.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.407-418
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• 2014

As the high-throughput requirement in the next generation communication system increases, it becomes essential to implement high-throughput SISO (Soft-Input Soft-Output) decoder with minimal hardware resources. In this paper, we present the comparison results between cascaded radix-4 ACS (Add-Compare-Select) and LUT (Look-Up Table)-based radix-4 ACS in terms of delay, area, and power consumption. The hardware overhead incurred from the retiming technique used for high speed radix-4 ACS operation is also analyzed. According to the various analysis results, high-throughput radix-4 SISO decoding architecture based on simple path metric recovery circuit is proposed to minimize the hardware resources. The proposed architecture is implemented in 65 nm CMOS process and memory requirement and power consumption can be reduced up to 78% and 32%, respectively, while achieving high-throughput requirement.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.21-25
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• 2017

In this study, we have fabricated Schottky barrier diodes (SBD) on single-crystal ${\beta}-Ga_2O_3$ semiconductor that has received much attention for use in next-generation power devices. The SBD had a Pt/Ti/Au Schottky contact on a $2{\mu}m$ Sn-doped low concentration N-type epitaxial layer. The fabricated device exhibited a breakdown voltage of > 180 V, a specific on-resistance of $1.26m{\Omega}{\cdot}cm^2$, and forward current densities of $77A/cm^2$ at 1 V and $473A/cm^2$ at 1.5 V, which proved the potential for use in power device fabrication.