• 제목/요약/키워드: New Address

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High Speed Driving Technique in AC PDPs

  • Shin, Bhum-Jae
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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    • pp.1181-1184
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    • 2007
  • The new self-priming addressing driving scheme was proposed to improve an address discharge time lag. It utilizes the priming effect maintaining the priming ramp discharge during an address period and the address discharge time lag is significantly improved. In this study, the basic characteristics of the priming ramp discharge are presented.

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Adaptive Partition-Based Address Allocation Protocol in Mobile Ad Hoc Networks

  • Kim, Ki-Il;Peng, Bai;Kim, Kyong-Hoon
    • Journal of information and communication convergence engineering
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    • 제7권2호
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    • pp.141-147
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    • 2009
  • To initialize and maintain self-organizing networks such as mobile ad hoc networks, address allocation protocol is essentially required. However, centralized approaches that pervasively used in traditional networks are not recommended in this kind of networks since they cannot handle with mobility efficiently. In addition, previous distributed approaches suffer from inefficiency with control overhead caused by duplicated address detection and management of available address pool. In this paper, we propose a new dynamic address allocation scheme, which is based on adaptive partition. An available address is managed in distributed way by multiple agents and partitioned adaptively according to current network environments. Finally, simulation results reveal that a proposed scheme is superior to previous approach in term of address acquisition delay under diverse simulation scenarios.

AC PDP의 장방전 구조의 구동을 위한 새로운 리셋파형 (New Reset Waveform for a Large-Sustain-Gap Structure in AC PDPs)

  • 김선;김동훈;송태용;김지용;이석현;서정현
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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    • pp.1544-1545
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    • 2006
  • In this paper, we present a new reset waveform for a large-sustain-gap structure in at PDPs. In the driving of the large-sustain-gap structure with a conventional ramp reset waveform, we cannot avoid the condition of an address being a cathode, which causes lots of trouble in stabilizing a reset discharge. To solve these problems, we use the square pulse instead of the conventional rising ramp pulse. Before making a strong discharge between the address (cathode) and scan (anode) electrodes, we make a priming discharge between the address (anode) and the scan (cathode) electrodes to stabilize the strong discharge in which the address electrodes are the cathode. With this scheme, we obtained 60V minimum address voltage and 145V maximum address voltage in $250{\mu}m$ and $350{\mu}m$ gap structures.

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다양한 블럭 크기를 갖는 섹터 캐시 메모리의 Trace-driven 시뮬레이션 알고리즘 (A New trace-driven Simulation Algorithm for Sector Cache Memories with Various Block Sizes)

  • Dong Gue Park
    • 전자공학회논문지B
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    • 제32B권6호
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    • pp.849-861
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    • 1995
  • In this paper, a new trace driven simulation algorithm is proposed to evaluate the bus traffic and the miss ration of the various sector cache memories, which have various sub-block sizes and block sizes and associativities and number of sets, with a single pass through an address trace. Trace-driven simulaton is usually used as a method for performance evaluation of sector cache memories, but it spends a lot of simulation time for simulating the diverse cache configurations with a long address trace. The proposed algorithm shortens the simulation time by evaluating the performance of the various sector cache configurations. which have various sub-block sizes and block sizes and associativities and number of sets , with a single pass through an address trace. Our simulation results show that the run times of the proposed simulation algorithm can be considerably reduced than those of existing simulation algorithms, when the proposed algorithm is miplemented in C language and the address traces obtained from the various sample programs are used as a input of trace-driven simulation.

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A New High Speed Addressing Method Using The Priming Effect in AC PDP

  • Kim, Jae-Sung;Yang, Jin-Ho;Kim, Tae-Jun;Whang, Ki-Woong
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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    • pp.105-108
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    • 2003
  • A new high speed addressing method is proposed to reduce the addressing time below lus per line in AC PDP. In this method, the priming discharge is used to achieve a high speed addressing without adding an auxiliary electrode. Two different types of priming discharges were studied to achieve a high speed addressing and also reduce the inherent light output caused by the priming discharge in order to improve the contrast ratio characteristics. In the panel experiment, the addressing was successfully done with a lus address pulse width in the new method and the better contrast ratio was achieved in the Y-A priming rather than the Y-X priming case even though the reduction of the address period was smaller than that of the Y-X priming due to the extra address time for the priming discharges.

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A new ramp reset waveform for reducing reset period using address pulse of AC-PDP

  • Kim, Gun-Su;Choi, Hoon-Young;Lee, Seok-Hyun;Kim, Jun-Hyoung;Mim, Byoung-Kuk
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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    • pp.609-612
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    • 2002
  • A new reset waveform is proposed for reducing the reset period. A square pulse is applied to the address electrode while reset pulse ramps and before a discharge between the sustain electrodes occurs. The square pulse induces a discharge between the address electrode and the X electrode, and the induced wall charge is opposite to the applied ramp pulse. Thus, the next discharge between the sustain electrodes becomes weaker. The weaker discharge lowers background luminance and improves contrast ratio. Thus, the new reset waveform can reduce ramp up time in the ramp reset waveform The experimental results show that the ramp up time can be reduced by about 90% compared with the conventional ramp reset waveform.

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내비게이션 지도 건물 갱신을 위한 도로명주소 지도와의 연계 방법에 대한 연구 (Study on method of linking with navigation map and new address map for updating navigation Map buildings)

  • 김기락;허용;유기윤
    • 한국측량학회:학술대회논문집
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    • 한국측량학회 2010년 춘계학술발표회 논문집
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    • pp.23-25
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    • 2010
  • In this paper, we studied linking method for updating navigation map with new address map. This method is hierarchical as we chose candidate using attribute data for geometry matching. Limiting a matching range, we conducted a experiment ICP with geometry matching. As a result, for linking method it's quite satisfied but for updating method, we decided that we have to do more precise method for updating.

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A Duplicate Address Resolution Protocol in Mobile Ad Hoc Networks

  • Lin Chunhung Richard;Wang Guo-Yuan Mikko
    • Journal of Communications and Networks
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    • 제7권4호
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    • pp.525-536
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    • 2005
  • In an IP-based network, automated dynamic assignment of IP addresses is preferable. In most wired networks, a node relies on a centralized server by using dynamic host configuration protocol (DHCP) to obtain a dynamic IP address. However, the DHCP­based approach cannot be employed in a mobile ad hoc network (MANET) due to the uncertainty of any centralized DHCP server. That is, a MANET may become partitioned due to host mobility. Therefore, there is no guarantee to access a DHCP server. A general approach to address this issue is to allow a mobile host to pick a tentative address randomly, and then use duplicate address resolution (DAR) protocol to resolve any duplicate addresses. In this paper, an innovative distributed dynamic host configuration protocol designed to configure nodes in MANET is presented. The proposed protocol not only can detect the duplicate address, but also can resolve the problem caused by duplicate address. It shows that the proposed protocol works correctly and is more universal than earlier approaches. An enhanced version of DAR scheme is also proposed in this paper to solve the situation of duplicate MAC address. The new and innovative approach proposed in this paper can make the nodes in MANET provide services to other networks and avoid packets from being delivered to incorrect destinations.

Linked-list 구조를 갖는 ATM용 공통 버퍼형 메모리 스위치 설계 (Design of a shared buffer memory switch with a linked-list architecture for ATM applications)

  • 이명희;조경록
    • 한국통신학회논문지
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    • 제21권11호
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    • pp.2850-2861
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    • 1996
  • This paper describes the design of AATM switch LIS of shared buffer type with linked-list architecture to control memory access. The proposed switch LSI consists of the buffer memory, controller and FIFO memory blocks and two special circuits to avoid the cell blocking. One of the special circuit is a new address control scheme with linked-list architecture which maintains the address of buffer memory serially ordered from write address to read address. All of the address is linked as chain is operated like a FIFO. The other is slip-flag register it will be hold the address chain when readaddress missed the reading of data. The circuits control the buffer memory efficiently and reduce the cell loss rate. As a result the designed chip operates at 33ns and occupied on 2.7*2.8mm$^{2}$ using 0.8.mu.m CMOS technology.

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