• 전자공학회논문지
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• 제50권7호
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• pp.131-139
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• 2013

기존 전기적 상호 연결을 사용한 네트워크-온-칩(Network-on-Chip, NoC)의 전력 및 성능 한계를 보완하고자 광학적 상호연결을 이용하는 하이브리드 광학 네트워크-온-칩(HONoC)이 등장하였다. 하지만 HONoC에서는 광학적 소자 특성으로 인해 서킷 스위칭을 사용함으로써 경로 충돌이 빈번하게 발생하며 이로 인해 지연 시간 불균형의 문제가 심화되어 전체적인 시스템 성능에 악영향을 미치게 된다. 본 논문에서는 경로 충돌을 최소화 시켜 지연 시간을 최적화 할 수 있는 새로운 태스크 매핑 알고리즘을 제안하였다. HONoC 환경에서 태스크를 각 Processing Element (PE)에 할당하고 경로 충돌을 최소화하며, 부득이한 경로 충돌의 경우 워스트 케이스 (worst case) 지연 시간을 최소화 할 수 있도록 하였다. 모의실험 결과를 통해 무작위 매핑 방식, 대역폭 제한 매핑 방식과 비교하여, 제안된 알고리즘이 $4{\times}4$ 메시 토폴로지에서는 평균 43%, $8{\times}8$ 메시 토폴로지에서는 평균 61%의 지연 시간 단축 효과가 있음을 확인할 수 있었다.

• 제어로봇시스템학회논문지
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• 제5권8호
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• pp.995-1000
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• 1999

This paper presents a optic system and a visual inspection algorithm looking for solder joint defects of J-lead chip which are more integrate and smaller than ones with Gull-wing on PCBs(Printed Circuit Boards). The visual inspection system is composed of three sections : host PC, imaging and driving parts. The host PC part controls the inspection devices and executes the inspection algorithm. The imaging part acquires and processes image data. And the driving part controls XY-table for automatic inspection. In this paper, the most important five features are extracted from input images to categorize four classes of solder joint defects in the case of J-lead chip and utilized to a back-propagation network for classification. Consequently, good accuracy of classification performance and effectiveness of chosen five features are examined by experiment using proposed inspection algorithm.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.457-458
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• 2007

We investigated a resistor network model for the horizontal AlInGaN LED. Adding the proposed current density dependent relative quantum efficiency, the power simulation can be also obtained. Comparing the simulation and the measurement results for the LED with the size of $350{\mu}m$, the model is reasonable to simulate the forward voltage and the light output power. Using this model we investigated the optimization of the position and the number of the finger electrodes in a given chip area. It shows that the center disposition of the p-finger electrode in p-area is optimal for the voltage and best for the power. And the minimum number of the n-finger electrodes is best for the power.

• 한국응용약물학회:학술대회논문집
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• 한국응용약물학회 2002년도 창립10주년기념 및 국립독성연구원 의약품동등성평가부서 신설기념 국재학술대회:생물학적 동등성과 의약품 개발 전략을 위한 국제심포지움
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• pp.73-78
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• 2002

Microfluidic lab-on-a-chip (LOC) systems have enabled a new generation ofassay technologies in chemical and biomedical sciences. Caliper's microfluidic LOC systems contain a network of microscopic channels through which fluids and chemical are moved in order to perform experiments. The main advantages of these continuous-flow devices are integration and automation of multiple steps in complex analytical procedures to improve the reproducibility of the results, and eliminated the manual labor, time and pipetting errors involved in analyses. The present talk is devoted to give a brief introduction of microfluidic basics and to present in applying continuous-flow microchips to drug screening with model enzyme assays.

• ETRI Journal
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• 제38권6호
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• pp.1240-1249
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• 2016

With the number of IP cores in a multicore system-on-chip increasing to up to tens or hundreds, the role of on-chip interconnection networks is vital. We propose a networks-on-chip-style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade-off for the time saving, the time cost (TC) of the searched architecture is increased to up to 4.7% and 11.2%, respectively, at each step compared with that of the architecture obtained through full-case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to 13.1% when compared with that obtained through full-case exploration.

• 대한전자공학회논문지SD
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• 제45권4호
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• pp.117-123
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• 2008

본 논문에서는 규칙적인 형태의 NoC 중 mesh 구조를 기반으로 한 어플리케이션 코어 매핑 알고리즘 연구 내용을 소개한다. 제안된 알고리즘은 ant colony optimization(ACO) 기법을 이용하여 주어진 SoC 내장 코어 및 NoC 특성 정보를 대상으로 가장 효과적인 코어 배치 결과를 도출한다. 설계 목적으로 사용된 네트워크 지연 시간 측정을 위해 평균 흡수 계산 결과를 이용하였으며 제한 조건으로는 NoC 대역폭을 기준으로 하였다. 12개의 코어로 구성되는 실제 기능 블럭을 대상으로 실험한 결과 계산 시간이나 매핑 결과 모두 우수함을 확인할 수 있었다.

• 전기학회논문지
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• 제61권2호
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• pp.347-353
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• 2012

In this paper, authors will develop the quick and precise remote controller of automatic fire detection equipment (P-type one-class receiver) based on information communication technology (IT). The remote controller detects the fire and disaster in the building automatically and quickly and then activates the facilities to extinguish the fire and disaster, monitoring such situation in a real time through wire-wireless communication network. The proposed remote controller is applied a programmable logic device (PLD) micom. of one-chip type which is small size and lightweight and also has highly sensitive-precise reliabilities. The one-chip type PLD micom. analyzes digital signals from sensors, then activates fire extinguishing facilities for alarm and rapid suppression in a case of fire and disaster. The detected data is also transferred to a remote situation room through wire-wireless network of RS232c and bluetooth communication, and then the situation room sends an emergency alarm signal. The automatic fire detection equipment (AFDE) based on IT will minimize the life and wealth loss while prevents fire and disaster.

• IEIE Transactions on Smart Processing and Computing
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• 제5권2호
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• pp.71-76
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• 2016

A controller area network (CAN) receiver measures differential voltage on a bus to determine the bus level. Since 3.3V transceivers generate the same differential voltage as 5V transceivers (usually ${\geq}1.5V$), all transceivers on the bus (regardless of supply voltage) can decipher the message. In fact, the other transceivers cannot even determine or show that there is anything different about the differential voltage levels. A new CMOS RC oscillator insensitive supply voltage for clock generation in a CAN transceiver was fabricated and tested to compensate for this drawback in CAN communication. The system consists of a symmetrical circuit for voltage and current switches, two capacitors, two comparators, and an RS flip-flop. The operational principle is similar to a bistable multivibrator but the oscillation frequency can also be controlled via a bias current and reference voltage. The chip test experimental results show that oscillation frequency and power dissipation are 500 kHz and 5.48 mW, respectively at a supply voltage of 3.3 V. The chip, chip area is $0.021mm^2$, is fabricated with $0.18{\mu}m$ CMOS technology from SK hynix.

• Journal of electromagnetic engineering and science
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• 제11권4호
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• pp.282-289
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• 2011

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2002년도 ICCAS
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• pp.89.4-89
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• 2002

$\textbullet$ Field Programmable Gate Array $\textbullet$ flexible hardware $\textbullet$ neural network $\textbullet$ determinism learning $\textbullet$ multi-valued logic $\textbullet$ disjunctive normal form $\textbullet$ multi-dimensional exclusive OR