• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.832-841
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• 2016

The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the on-chip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.

• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.89-103
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.120-136
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.104-119
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• Molecules and Cells
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• v.45 no.2
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• pp.76-83
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• 2022

Neurons-on-a-Chip technology has been developed to provide diverse in vitro neuro-tools to study neuritogenesis, synaptogensis, axon guidance, and network dynamics. The two core enabling technologies are soft-lithography and microelectrode array technology. Soft lithography technology made it possible to fabricate microstamps and microfluidic channel devices with a simple replica molding method in a biological laboratory and innovatively reduced the turn-around time from assay design to chip fabrication, facilitating various experimental designs. To control nerve cell behaviors at the single cell level via chemical cues, surface biofunctionalization methods and micropatterning techniques were developed. Microelectrode chip technology, which provides a functional readout by measuring the electrophysiological signals from individual neurons, has become a popular platform to investigate neural information processing in networks. Due to these key advances, it is possible to study the relationship between the network structure and functions, and they have opened a new era of neurobiology and will become standard tools in the near future.

• ETRI Journal
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• v.36 no.3
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• pp.367-373
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• 2014

With high bandwidth, low interference, and low power consumption, optical network-on-chip (ONoC) has emerged as a highly efficient interconnection for the future generation of multicore system on chips. In this paper, we propose a new path-setup method for ONoC to mitigate contentions, such as packets, by recycling the setup packet halfway to the destination. A new, strictly non-blocking $6{\times}6$ optical router is designed to support the new method. The simulation results show the new path-setup method increases the throughput by 52.03%, 41.94%, and 36.47% under uniform, hotspot-I, and hotspot-II traffic patterns, respectively. The end-to-end delay performance is also improved.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.259-269
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• 2012

With the lower supply voltage and the higher operating frequency in integrated circuits, the analysis of the power distribution network (PDN) including on-chip inductances becomes more important. In this paper, an effective inductance extraction method for a regular on-chip power grid structure is proposed. The loop inductance model applicable to chip layout is proposed and the inductance extraction tool using the proposed inductance model based on post layout RC circuits is developed. The accuracy of the proposed loop model and the developed tool is verified by comparing the test circuit simulation results with those from the partial element equivalent circuit (PEEC) model. The voltage fluctuation from the RLC circuits extracted by the developed tool was examined for the analysis of on-chip inductance effects. The significance of on-chip power grid inductance was investigated by the co-simulation of chip-package-PCB.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.146-150
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• 2001

Microwave model and high-frequency measurement of the ACF flip-chip interconnection was investigated using a microwave network analysis. S-parameters of on-chip and substrate were separately measured in the frequency range of 200 MHz to 20 GHz using a microwave network analyzer HP8510 and cascade probe. And the cascade transmission matrix conversion was performed. The same measurements and conversion techniques were conducted on the assembled test chip and substrate at the same frequency range. Then impedance values in ACF flip-chip interconnection were extracted from cascade transmission matrix. ACF flip chip interconnection has only below 0.1nH, and very stable up to 13 GHz. Over the 13 GHz, there was significant loss because of epoxy capacitance of ACF. However, the addition of SiO$_2$filler to the ACF lowered the dielectric constant of the ACF materials resulting in an increase of resonance frequency up to 15 GHz. High frequency behavior of metal Au stud bumps was investigated. The resonance frequency of the metal stud bump interconnects is higher than that of ACF flip-chip interconnects and is not observed at the microwave frequency band. The extracted model parameters of adhesive flip chip interconnects were analyzed with the considerations of the characteristics of material and the design guideline of ACA flip chip for high frequency applications was provided.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.80-88
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• 2007

High adaptability and scalability are two critical issues in implementing a very complex system in a single chip. To obtain high adaptability and scalability, novel system design methodology known as communication-based system design has gained large attention from SoC designers. NoC (Network-on-Chip) is such an on-chip communication-based design approach for the next generation SoC design. To provide high adaptability and scalability, NoCs employ network interfaces and routers as their main communication structures and transmit and receive packetized data over such structures. However, data packetization, and routing overhead in terms of run time and area may cost too much compared with conventional SoC communication structure. Therefore, in this research, we propose a novel methodology which automatically generates a hybrid communication structure. In this work, we map traditional pin-to-pin wiring structure for frequent and timing critical communication, and map flexible and scalable structure for infrequent, or highly variable communication patterns. Even though, we simplify the communication structure significantly through our algorithm the connectivity or the scalability of the communication modules are almost maintained as the original NoC design. Using this method, we could improve the timing performance by 49.19%, and the area taken by the communication structure has been reduced by 24.03%.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.869-872
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• 2005

In this paper we present a switch wrapper for an AMBA AXI, which is an efficient on-chip-network interface compared to bus-based interfaces in a multiprocessor SoC. The AXI uses an idea of NoC to provide the increasing demands on communication bandwidth within a single chip. A switch wrapper for AXI is located between a interconnection network and two IPs connecting them together. It carries out a mode of routing to interconnection network and executes protocol conversions to provide compatibility in IP reuse. A switch wrapper consists of a direct router, AHB-AXI converters, interface modules and a controller modules. We propose the design of a all-in-one type switch wrapper.