• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1243-1248
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• 2008

As development in technology of bioinformatics recently mates it possible to operate micro-level experiments, we can observe the expression pattern of total genome through on chip and analyze the interactions of thousands of genes at the same time. In this thesis, we used CDNA microarrays of 3840 genes obtained from neuronal differentiation experiment of cortical stem cells on white mouse with cancer. It analyzed and compared performance of each of the experiment result using existing DT, NB, SVM and multi-perceptron neural network classifier combined the similar scale combination method after constructing class classification model by extracting significant gene list with a similar scale combination method proposed in this paper through normalization. Result classifying in Multi-Perceptron neural network classifier for selected 200 genes using combination of PC(Pearson correlation coefficient) and ED(Euclidean distance coefficient) represented the accuracy of 98.84%, which show that it improve classification performance than case to experiment using other classifier.

• Journal of IKEEE
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• v.28 no.2
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• pp.234-238
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• 2024

This paper presents a study on the integration of 3D-stacked dual-tip RRAM with a CNN accelerator architecture, leveraging its low drive current characteristics and scalability in a 3D stacked configuration. The dual-tip structure is utilized in a parallel connection format in a synaptic array to implement multi-level capabilities. It is configured within a Network-on-chip style accelerator along with various hardware blocks such as DAC, ADC, buffers, registers, and shift & add circuits, and simulations were performed for the CNN accelerator. The quantization of synaptic weights and activation functions was assumed to be 16-bit. Simulation results of CNN operations through a parallel pipeline for this accelerator architecture achieved an operational efficiency of approximately 370 GOPs/W, with accuracy degradation due to quantization kept within 3%.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.417-420
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• 2002

In this paper, we implemented a SDH synchronous network system based on ITU-T recommendation G.707 - Network node interface for the synchronous digital archy(SDH). For the system, we used signal processing SDH ASIC, and designed a FPGA_Control chip for various signal control and a FPGA_Alignment cllip for data alignment using YHDL(Very high speed integrated circuit Hardware Description Language). For system monitoring, an operation system was developed using ANSI C and executed in CPU (Motorola MPC-860). The system was evaluated by using ANT-20 for data transmission error defection, jitter detection, pointer chocking, and overhead determination.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.10
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• pp.62-70
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• 1996

We experimented on cutting characteristics-cutting force, behavior of cutting temperature, surface roughness. chip thickness under low temperature, which generated by liquid nitrogen(77K). The work-pieces were freezed to-195 .deg. C and liquid nitrogen was also sprinkled on cutting area in order to decrease an experimental error of machining in low temperature. The workpiece was became to -195 .deg. C in5 minutes. In cooled condition surface roughness of workpiece was better than normal condition. In addition, we investigated the possibility that surface roughness of workpiece and cutting force can be predicted analyzing cutting conditions by the trained neural network.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1687-1693
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• 2007

Advances in technologies of networking, chip integration, and embedded system have enabled sensor networks applicable to a wide range of areas. Sharing some common characteristics, sensor networks are thus diversified in features depending on their applications. An intelligent and digital home can be one area to establish a particular feature of sensor network. This paper proposes a composite sensor and control network, and discusses its applying to the next generation intelligent and digital home. Development results of the network and a test-bed as a virtual test environment are also presented. The proposed network can not only be efficiently applying to achieve new home intelligences but also provide a sound solution to maintenance and operations of home network or devices.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.411-414
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• 2004

This paper introduces a modulation method for digital wireless communication based on general DS-QPSK. The design and fabrication is for home networking application to a typical RF transmitter with DS-QPSK modulator. This modulator implemented using VHDL hardware programming language, the fabrication of IC chip $5{\times}5 mm^2$ was carried by 27th IDEC MPW(Multi Project Wafer) process in 0.35${\mu}m$ rule at Samsung Inc. This paper presented the important of this technology for the future application in wireless sensor. This module can be efficient usage for home network to transmit the RF wireless sensor system.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.05a
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• pp.404-411
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• 2004

With distribution industrial control system, the use of low cost to achieve a highly reliable and safe system in real time distributed embedded application is proposed. This developed intelligent node is based on two microcontrollers, one for the execution of the application code, also as master controller for ensuring the real time control & the logic operation with CPLD and other for communication task and the easy control execution, i.e., I/O digital input, digital output and interrupting. This paper also presents where the case NCS (Networked control system) with LonTalk protocol is applied for the filtration process control system of a small water treatment plant.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.7 no.1
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• pp.10-17
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• 1982

Recently, there has been a great interest in the realization of analog fiters using switched and fixed capacitors and active elements. It is known that a switched capacitor has an performance much better that a resistor in the characteristics of temperature and linearity, and can be fabricated on the much smaller area than the resistor. In this paper all the resistors in the gyrator filter network are relpaced by the switched capacitors for an SC-Gyrator filter circuit can be fully integrated into a single chip by using MOS technology. By experiments we show that the response of designed SC-Gyrator filter is much similar to that of its protorype gyrator filter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.167-174
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• 2003

This paper proposes a network processor especially optimized for content switching. With 2Gbps port capability, it integrates packet processor cluster, content-based classification engine and traffic manager on a single chip. A switch fabric architecture is also designed for scale-up of the network processor's capability over hundreds gigabit bandwidth. Applied in real network systems, the network processor shows wire-speed network address translator (NAT) and content-based switching performance.