• International Journal of Precision Engineering and Manufacturing
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• 제4권6호
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• pp.5-11
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• 2003

The number of the enterprises which utilize network technology has been increasing for solving problems such as productivity improvement, market trend analysis, and material collection for making decision. Especially, the management of equipment and the recovery time reduction when machines break down are very important factors in productivity improvement of the enterprise. Currently, most of the remote trouble diagnosis of equipment using the internet have just one function of transmitting the trouble information to the user. Therefore it does not directly reflect the user's recovery experience or the developer's new recovery methods. If the user's experienced recovery methods or the developer's recovery methods as well as the basic recovery methods are reflected online or on the internet, it makes it possible to recover faster than before. In this paper, we develop a Remote Monitoring Server (RMS) for chip mounters, and make it possible to reduce the recovery time by reflecting the user's experience and developer's new methods in addition to presenting the basic recovery methods. For this, trouble recovery concept will be defined. Based on this, many functions(trouble diagnosis, the presentation of the basic recovery methods, user's and developer's recovery method, counting function of the trouble number of each code, and presentation of usage number of each recovery methods) were developed. By utilizing the reports of the actual results of chip mounter and the notice function of the parts change time, the rate of operation of the chip mounter can be improved.

• ETRI Journal
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• 제35권5호
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• pp.767-774
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• 2013

In this paper, a novel parallel Viterbi decoding scheme is proposed to decrease the decoding latency and power consumption for the software-defined radio (SDR) system. It implements a divide-and-conquer approach by first dividing a block into a series of subblocks, then performing independent Viterbi decoding for each subsequence, and finally merging the surviving subpaths into the final path. Moreover, a network-on-chip-based SDR platform is used to evaluate the performance of the proposed parallel Viterbi decoding scheme. The experiment results show that our scheme can speed up the Viterbi decoding process without increasing the BER, and it performs better than the current state-of-the-art methods.

• ETRI Journal
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• 제35권3호
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• pp.554-557
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• 2013

This letter presents a power amplifier (PA) with an on-chip power detector for 2.4-GHz wireless local area network application. The power detector consists of a clamp circuit, a diode detector, and a coupled line directional coupler. A series inductor for an output matching network in the PA is combined with a through line of the coupler, which reduces the coupling level. Therefore, the coupler employs a metamaterial-based transformer configuration to increase coupling. The amount of coupling is increased by 2.5 dB in the 1:1 symmetric transformer structure and by 4.5 dB from two metamaterial units along the coupled line.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1931_1933
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• 2009

NoC 기반 시스템이 적용되는 설계는 시스템 크기가 커짐에 따라 칩 테스트 문제도 동시에 제기 되고 있다. 이에 따라 NoC 기반의 시스템의 테스트 시간을 줄일 수 있는 internal test 방식의 새로운 BIST(Built-in Self-Test) 구조에 관한 연구를 하였다. 기존의 NoC 기반 시스템의 BIST 테스트 구조는 각각의 router와 core에 BIST logic과 random pattern generator로 LFSR(Linear Feedback Shift Register)을 사용하여 연결하는 individual 방식과 하나의 BIST logic과 LFSR을 사용하여 각각의 router와 core에 병렬로 연결하는 distributed 방식을 사용한다. 이때, LFSR에서 생성된 테스트 벡터가 router에 사용되는 FIFO 메모리를 통과하면서 생기는 테스트 타임 증가를 줄이기 위하여 shift register 형태의 FIFO 메모리를 변경하였다 제안된 방법에서 테스트 커버리지 98%이상을 달성하였고, area overhead면에서 효과를 볼 수 있다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 Proceedings of 6th International Joint Symposium on Microeletronics and Packaging
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• pp.35-43
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• 2001

Flip chip assembly on organic substrates using ACAs have received much attentions due to many advantages such as easier processing, good electrical performance, lower cost, and low temperature processing compatible with organic substrates. ACAs are generally composed of epoxy polymer resin and small amount of conductive fillers (less than 10 wt.%). As a result, ACAs have almost the same CTE values as an epoxy material itself which are higher than conventional underfill materials which contains lots of fillers. Therefore, it is necessary to lower the CTE value of ACAs to obtain more reliable flip chip assembly on organic substrates using ACAs. To modify the ACA composite materials with some amount of conductive fillers, non-conductive fillers were incorporated into ACAs. In this paper, we investigated the effect of fillers on the thermo-mechanical properties of modified ACA composite materials and the reliability of flip chip assembly on organic substrates using modified ACA composite materials. Contact resistance changes were measured during reliability tests such as thermal cycling, high humidity and temperature, and high temperature at dry condition. It was observed that reliability results were significantly affected by CTEs of ACA materials especially at the thermal cycling test. Results showed that flip chip assembly using modified ACA composites with lower CTEs and higher modulus by loading non-conducting fillers exhibited better contact resistance behavior than conventional ACAs without non-conducting fillers. Microwave model and high-frequency measurement of the ACF flip-chip interconnection was investigated using a microwave network analysis. ACF flip chip interconnection has only below 0.1nH, and very stable up to 13 GHz. Over the 13 GHz, there was significant loss because of epoxy capacitance of ACF. However, the addition of $SiO_2filler$ to the ACF lowered the dielectric constant of the ACF materials resulting in an increase of resonance frequency up to 15 GHz. Our results indicate that the electrical performance of ACF combined with electroless Wi/Au bump interconnection is comparable to that of solder joint.

• 한국생물공학회:학술대회논문집
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• 한국생물공학회 2003년도 생물공학의 동향(XIII)
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• pp.717-720
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• 2003

A chromogenic biosensor employing microfluidics on a chip has been developed for the determination of high-density lipoprotein (HDL) cholesterol (HDL-C) in human serum. We have investigated a plain and effective method to immobilize enzymes within the microchip without chemically modifying micro-channel or technically micro-fabricating column reactor and fluid channel network. In assessing risk factors of coronary heart disease, a micro-chip system would minimize requirements of instrument and reagent handling.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.1137-1140
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• 1999

In this thesis, we research about Communication System Construction and Test-Bed Realization Method and Software’s Design with written program into Embedded Micro Controller’s restricted memory region using a DSP Chip to deal with mainly high speed communication. Tools used for modern communication network control use TI or AMD general chip class, but nevertheless responsibility for the point at issue, Analog Device is architecture design model moderated for small communication system. In this thesis, we present extended model, and realize basic case.

• 대한전자공학회논문지SD
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• 제39권9호
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• pp.37-44
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• 2002

학습된 신경망(Pre-trained neural network)은 고정된 가중치(weight)를 갖는다. 이 논문에서는 이러한 특성을 이용하여 신경망의 효과적인 디지털 하드웨어의 설계방법을 제안한다. 이를 위해 신경망의 PEs(Processing Elements)연산은 행렬-벡터 곱셈으로 표하고 고정된 가중치와 입력 데이터의 관계를 비트-레벨 어레이(array) 구조로 표현하여, 노드 소거와 가중치 비트 패턴에 따른 공유 노드 설정을 통한 최적화로 연산에 필요한 노드를 최소화한다. FPGA 시뮬레이션 결과, 완전한 정확성에 기반한 하드웨어를 설계하는 경우, 하드웨어 비용을 상당부분 줄였고 동작 주파수가 높다는 것을 확인하였다. 또한, 제안한 설계방법은 한정된 공간 내에서 많은 수의 PEs 구현이 가능함으로, 큰 신경망 모델에 대한 온-칩(on-chip) 구현이 가능하다.

• 전자공학회논문지B
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• 제33B권3호
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• pp.186-192
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• 1996

A modified learning rule is introduced for the implementation of feedforward artificial neural networks with on-chip learning circuitry using standard analog CMOS technology. Learning rule, is modified form the EBP (error back propagation) rule which is one of the well-known learning rules for the feedforward rtificial neural nets(FANNs). The employed MEBP ( modified EBP) rule is well - suited for the hardware implementation of FANNs with on-chip learning rule. As a ynapse circuit, a four-quadrant vector-product linear multiplier is employed, whose input/output signals are given with voltage units. Two $2{\times}2{\times}1$ FANNs are implemented with the learning circuitry. The implemented FANN circuits have been simulatied with learning test patterns using the PSPICE circuit simulator and their results show correct learning functions.

• 유체기계공업학회:학술대회논문집
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• 유체기계공업학회 2006년 제4회 한국유체공학학술대회 논문집
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• pp.305-308
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• 2006

For controlling micro-flows inside a LOC (lab-on-a-chip) a syringe pump or an electronic device for EOF(electro-osmotic flow) have been used in general. However, these devices are so large and heavy that they are burdensome in the development of a portable micro-TAS (total analysis system). In this study, a new flow control system employing pressure chambers, digital switches and speed controllers was developed. This system could effectively control the micro-scale flows inside a LOC without any mechanical actuators or electronic devices We also checked the feasibility of this new control system by applying it to a LOC of micro-mixer type. Performance tests show that the developed control system has very good performance. Because the flow rate in LOC is controlled easily by throttling the speed controller, the flows in complicate microchannels network can be also controlled precisely.