• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.1202-1208
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• 1995

Inter-processor communication is required to manage resources in ATM switching system where processors are distributed. ATM switching system, which was developed in our institute, does't have dedicated communication path for inter-processor communication, but use the ordinary switching network same as user data. Therefore, we should test communication paths and equipments before running various application software programs. In this paper, we propose a method to test communication paths between processors in ATM switching system and describe an implemented program using this method.

• Journal of Industrial Technology
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• v.15
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• pp.33-40
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• 1995

This paper presents a new method for load distribution in a single-level tree network equipped with front-end processors. This method focuses on effective data distribution over a number of processors minimize job processing time. Optimal multiple installment load distribution algorithm is presented. Minimum number of processors that maximizes efficiency is decided theoretically.

• Communications of the Korean Mathematical Society
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• v.10 no.3
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• pp.735-750
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• 1995

We present a domain decomposition algorithm for solving large sparse linear systems of equations arising from queuing networks. Such techniques are attractive since the problems in subdomains can be solved independently by parallel processors. Many of the methods proposed so far use some form of the preconditioned conjugate gradient method to deal with one large interface problem between subdomains. However, in this paper, we propose a "nested" domain decomposition method where the subsystems governing the interfaces are small enough so that they are easily solvable by direct methods on machines with many parallel processors. Convergence of the algorithms is also shown.lso shown.

• Proceedings of the Korea Inteligent Information System Society Conference
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• 2006.06a
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• pp.303-310
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• 2006

The sorting algorithms have been developed to take advantage of distributed computers. But the speedup of parallel sorting algorithms decrease rapidly with increased number of processors due to parallel processing overhead such as context switching time and inter-processor communication cost. In this paper, we propose a parallel sorting method which provides linear speedup of an optimal serial algorithm for a system with a large number of processors. This algorithm may even provide superlinear speedup for a practical system. The algorithm takes advantage of an interconnection network properties and its protocol.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.451-453
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• 2007

This paper describes the design of an asynchronous implementation of a sensor network processor. The main purpose of this work is the reduction of power consumption in sensor network node processors and the research presented here tries to explore the suitability of asynchronous circuits for this purpose. The Handshake Solutions toolkit is used to implement an asynchronous version of a sensor processor. The design is made compact, trading area and leakage power savings with dynamic power costs, targeting the typical sparse operating characteristics of sensor node processors. It is then compared with a synchronous version of the same processor. Both versions are then compared with existing commercial processors in terms of power consumption.

• Journal of information and communication convergence engineering
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• v.12 no.3
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• pp.145-153
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• 2014

The improvements of embedded processors make future technologies including wireless sensor network and internet of things feasible. These applications firstly gather information from target field through wireless network. However, this networking process is highly vulnerable to malicious attacks including eavesdropping and forgery. In order to ensure secure and robust networking, information should be kept in secret with cryptography. Well known approach is public key cryptography and this algorithm consists of finite field arithmetic. There are many works considering high speed finite field arithmetic. One of the famous approach is Montgomery multiplication. In this study, we investigated Montgomery multiplication for public key cryptography on embedded microprocessors. This paper includes helpful information on Montgomery multiplication implementation methods and techniques for various target devices including 8-bit and 16-bit microprocessors. Further, we expect that the results reported in this paper will become part of a reference book for advanced Montgomery multiplication methods for future researchers.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.10
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• pp.90-97
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• 1996

This paper presents an efficient parallel implementation and its performance evaluations of a SOFM neural netowrk on the multicomputer. We investigate the parallel performance as the size of a neural network N, the number of the patterns L, and the number of the processors p increase. We propose an analytica performance evaluation model for eac of the parallel implementations and verified the validity of the model through experiments. Analytical result show that the number of processors for a maximum speedup of the network decomposition nd the training-set decomposition increases in proportion to .root.N and .root.L, respectively. The performances of the both decompositions depend on the number of training patterns L and the size of the neural network N and, if L.geq.0.423N, the performance of trhe training-set decomposition is proved to be better than that of the network decomposition.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.44-50
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• 1997

This paper describes the design and test of an on-line non-invasive network performance monitor (hardware portion) for the SPAX parallel computer. The SPAX parallel computer supports up to 256 intel P6 processors with 4 P6 processors constituting a processign node. The nodes are interconnected with a dual two-level crossbar network calle dXcent-net. Since the performance of the SPAX parallel computer is highly dependent on the proper and efficient operation of the network, an on-line non-invasive network performance monitor (with hardware components) has been developed to aid in the monitoring and tunign of the Xcent-net. Successful testing of a prototype node monitor board and PC interface system shows that our monitor design provides a low-cost practical solution to this problem.

• The Transactions of the Korea Information Processing Society
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• v.7 no.5
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• pp.1370-1376
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• 2000

Consider the problem to updata breadth-First Spanning Tree in response to topology change of the network. The paper proposes an efficient distributed algorithm that solves such a problem after several processors and links are added and deleted. Its message complexity and its ideal-time complexity are O(p√q+q+a+n') respectively, where n' is the number fo processors in the network after the topology change, a is the number of added links, p is the total number of links in the biconnected component (of the network before the topology change) including the detected links or added links, and q is the total number of processors in the biconnected component (of the network before the topology change) including the deleted links or added links, and q is the total number of processors in the biconnected component including the deleted links or added links.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1211-1217
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• 2005

Current generation embedded systems are built around only a small number of SOCs, which are again based on general-purpose embedded micro-processors, such as ARM and MIPS. These RISC-based processors are not, however, designed for specific functions such as networking and multimedia processing, whose importances have increased dramatically in recent years. Network devices for small business and home networks, are especially dependent upon such SOCs based on general processors. Except for PHY and MAC layer functions, which are built with hardware, all the network functions are processed by the embedded micro-processor. Enabling technologies such as VDSL and FTTH promise Internet access with a much higher speed, while at the same time explore the limitations of general purpose microprocessors. In this paper we design a network processor, embed it into an SOC for Home gateway, evaluate the performance rigorously, and gauge a possibility for commercialization.