• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1004-1009
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• 2004

Precise time synchronization is a main technology in high-speed communications, parallel and distributed processing systems, Internet information industry and electronic commerce. Synchronized clocks are useful for many leasers. Often a distributed system is designed to realize some synchronized behavior, especially in real-time processing in factories, aircraft, space vehicles, and military applications. Nowadays, time synchronization has been compulsory thing as distributed processing and network operations are generalized. A network time server obtains, keeps accurate and precise time by synchronizing its local clock to standard reference time source and distributes time information through standard time synchronization protocol. This paper describes design issues and implementation of a network time server for time synchronization especially based on a clock model. The system uses GPS (Global Positioning System) as a standard reference time source and offers UTC (universal Time coordinated) through NTP (Network Time protocol). Implementation result and performance analysis are also presented.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.11 s.102
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• pp.1075-1085
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• 2005

The purpose of this paper is to design the architecture for synchronization of MB-OFDM UWB system that is being processed the standardization for Alt-PHY of WPAN(Wireless Personal Area Network) at IEEE802.15.3a and to analyze the implementation loss due to 4 parallel synchronization architecture for design or link margin. First an overview of the MB-OFDM UWB system based on IEEE802.15.3a Alt-PHY standard is described. The effects of non-ideal transmission conditions of the MB-OFDM UWB system including carrier frequency offset and sampling clock offset are analyzed to design a full digital architecture for synchronization. The synchronization architecture using 4-parallel structure is then proposed to consider the VLSI implementation including algorithms for carrier frequency offset and sampling clock offset to minimize the effects of synchronization errors. The overall performance degradation due to the proposed synchronization architecture is simulated to be with maximum 3.08 dB of the ideal receiver in maximum carrier frequency offset and sampling clock offset tolerance fir MB-OFDM UWB system.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.1
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• pp.61-66
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• 2005

Location Positioning is a major technology for ubiquitous computing. Recently the research on Location Positioning using UWB is on going. In order to construct an in-door location network, synchronization of base stations is very important. NTP is Popularly used as clock synchronization protocol ranging from LAN to WAN. Also Master-Slave scheme is the simplest method to synchronize in-door network. We compare and analyze NTP and Master-Slave schemes according to the statistical channel model for indoor multipath propagation environment. In this paper, error ranges are calculated at various circumstances that in-door network expands from one primary base station into several base stations. We compared the correctness of NTP and Master-Slave synchronization methods. NTP is more reasonable synchronization protocol in in-door environment.

• Journal of Institute of Control, Robotics and Systems
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• v.9 no.11
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• pp.963-968
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• 2003

A feedback control implementation for a high speed train pressurization system is proposed based on CAN (Controller Area Network). Firstly, system model including network latencies by CAN arbitration mechanisms is proposed, and an analytical compensation method of control parameters based on the system model is proposed for the network latencies. For the practical implementation of the control, global synchronization is adopted for controller to measure network latencies and to utilize them for the compensation of the control parameters. Simulation results are shown with practical tunnel data response. The proposed method is evaluated to be the most effective for the system through the control performances comparing among a controller not considering network latencies, other two off-line compensation methods, and the proposed method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.7
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• pp.4871-4877
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• 2015

This article presents a circuit and a system for IEEE 1588 based clock synchronization to generate a very accurate frequency signal required in femtocell devices. A prototype board and the experimental environment to verify the functions and to evaluate the performance are explained to verify the feasibility of the proposed synchronization system. To make low-cost femtocells without constraints on the place of installation, it is very important to study on the practical implementation of synchronization system based on IEEE 1588. The experimental result shows that the synchronization errors between -16 ns and 9 ns are guaranteed over the network of femtocell devices with the proposed synchronization circuits, thus the synchronization criteria of the 3GPP HNB are met.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.461-463
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• 2018

In this paper, we have studied the devices needed for long distance wireless transmission of SDH network. This devices propose wireless transmission and measurement method of STM-1(basic transmission unit of SDH method) signal and 200Mbps synchronous ethernet. The synchronous clock recovery function is provided for STM-N transmission and synchronous ethernet transmission, and spare clock switching function is designed for stable synchronization. In addition, we discussed the measurement method of STM-N and synchronous Etherent communication method in wireless transmission section.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5A
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• pp.561-570
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• 2008

Time synchronization is essential for a number of network applications such as high speed communication and parallel/distribution processing systems. As the era of ubiquitous computing is ushered in, the high precise time synchronization in wireless networks have been required in. This paper presents the design ana the implementation of the high precision time synchronization in wireless networks using ZigBee. To achieve high precision requirements, we have tried to analyze and reduce error factors such as the latency and jitters of a protocol stack on wireless environments. In addition, this paper includes some experiments and performance evaluations of our system. The result is that we established for nodes in a network to maintain their elects to within a 50 nanosecond offset from the reference clock.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.35-42
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• 2005

This paper describes novel flip-flops with improved robustness and reduced power consumption. Variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces power consumption for higher input switching activities as compared to the conventional low-power flip-flop. Clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) reduces clock power consumption by allowing the use of a small swing clock. Unlike conventional reduced clock swing flip-flops, it requires no additional voltage higher than the supply voltage, eliminating design overhead related to the generation and distribution of this voltage. Simulation results indicate that the proposed flip-flops provide uniform latency for narrower sampling window and improved power-delay product as compared to conventional flip-flops. To evaluate the performance of the proposed flip-flops, test structures were designed and implemented in a $0.3\mu m$ CMOS process technology. Experimental result indicates that VSWFF yields power reduction for the maximum input switching activity, and a synchronous counter designed with CSR-VSWFF improves performance in terms of power consumption with no use of extra voltage higher than the supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.