• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.10A
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• pp.922-929
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• 2005

This paper proposes an adaptive pilot beacon equipment for mobile communication systems based on direct spread spectrum technology which generates the pilot channel for handoff between base stations by using the information acquired from the downstream wireless signal regarding the overhead channel information. Such an adaptive pilot beacon equipment will enable low power operation since among the wireless signals, only the pilot channel will be generated and transmitted. The pilot channel in the downstream link of the CDMA receiver is used to acquire time and frequency synchronization and this is used to calibrate the offset for the beacon, which implies that time synchronization using GPS is not required and any location where forward receive signal can be received can be used as the installation site. The downstream link pilot signal searching within the CDMA receiver is performed by FPGA and DSP. The FPGA is used to perform the initial synchronization for the pilot searcher and DSP is used to perform the offset correction between beacon clock and base station clock. The CDMA transmitter the adaptive pilot beacon equipment will use the timing offset information in the pilot channel acquired from the CDMA receiver and generate the downstream link pilot signal synchronized to the base station. The intermediate frequency signal is passed through the FIR filter and subsequently upconverted and amplified before being radiated through the antenna.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.48-58
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• 2006

This paper presents 8x8 two dimensional DCT/IDCT processor of adder-based distributed arithmetic architecture without applying ROM units in conventional memories. To reduce hardware cost in the coefficient matrix of DCT and IDCT, an odd part of the coefficient matrix was shared. The proposed architecture uses only 29 adders to compute coefficient operation in the 2-D DCT/IDCT processor, while 1-D DCT processor consists of 18 adders to compute coefficient operation. This architecture reduced 48.6% more than the number of adders in 8x8 1-D DCT NEDA architecture. Also, this paper proposed a form of new transpose network which is different from the conventional transpose memory block. The proposed transpose network block uses 64 registers with reduction of 18% more than the number of transistors in conventional memory architecture. Also, to improve throughput, eight input data receive eight pixels in every clock cycle and accordingly eight pixels are produced at the outputs.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.78-89
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• 2013

This paper proposes a high-throughput and multi-mode quasi-cyclic (QC) low-density parity-check (LDPC) decoder based on a fully parallel structure. The proposed QC-LDPC decoder employs the fully parallel structure to provide very high throughput. The high interconnection complexity, which is the general problem in the fully parallel structure, is solved by using a broadcasting-based sum-product algorithm and proposing a low-complexity cyclic shift network. The high complexity problem, which is caused by using a large amount of check node processors and variable node processors, is solved by proposing a combined check and variable node processor (CCVP). The proposed QC-LDPC decoder can support the multi-mode decoding by proposing a routing-based interconnection network, the flexible CCVP and the flexible cyclic shift network. The proposed QC-LDPC decoder is operated at 100 MHz clock frequency. The proposed QC-LDPC decoder supports multi-mode decoding and provides 8.1 Gbps throughput for a (1944, 1620) QC-LDPC code.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.10
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• pp.373-380
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• 2022

This paper presents a deep learning based group synchronization that supports networked immersive interactions between remote users. The goal of group synchronization is to enable all participants to synchronously interact with others for increasing user presence Most previous methods focus on NTP-based clock synchronization to enhance time accuracy. Moving average filters are used to control media playout time on the synchronization server. As an example, the exponentially weighted moving average(EWMA) would be able to track and estimate accurate playout time if the changes in input data are not significant. However it needs more time to be stable for any given change over time due to codec and system loads or fluctuations in network status. To tackle this problem, this work proposes the Deep Group Synchronization(DeepGroupSync), a group synchronization based on deep learning that models important features from the data. This model consists of two Gated Recurrent Unit(GRU) layers and one fully-connected layer, which predicts an optimal playout time by utilizing the sequential playout delays. The experiments are conducted with an existing method that uses the EWMA and the proposed method that uses the DeepGroupSync. The results show that the proposed method are more robust against unpredictable or rapid network condition changes than the existing method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1237-1245
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• 2006

This paper presented a hardware implementation of ARIA, which is a Korean standard l28-bit block cryptography algorithm. In this work, ARIA was designed technology-independently for application such as ASIC or core-based designs. ARIA algorithm was fitted in FPGA without additional components of hardware or software. It was confirmed that the rate of resource usage is about 19% in Altera EPXAl0F1020CI and the resulting design operates stably in a clock frequency of 36.35MHz, whose encryption/decryption rate was 310.3Mbps. Consequently, the proposed hardware implementation of ARIA is expected to have a lot of application fields which need high speed process such as electronic commerce, mobile communication, network security and the fields requiring lots of data storing where many users need processing large amount of data simultaneously.

• The Bulletin of The Korean Astronomical Society
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• v.40 no.1
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• pp.56.3-57
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• 2015

As of early 2015, more than 12,000 Near-Earth Objects (NEOs) have been catalogued by the Minor Planet Center, however their observational properties such as broadband colors and rotational periods are known only for a small fraction of the population. Thanks to time series observations with the KMTNet, orbits, optical sizes (and albedo), spin states and three dimensional shapes of asteroids and comets including NEOs will be systematically investigated and archived for the first time. Based on SDSS and BVRI colors, their approximate surface mineralogy will also be characterized. This so-called DEEP-South (Deep Ecliptic Patrol of the Southern Sky) project will provide a prompt solution to the demand from the scientific community to bridge the gaps in global sky coverage with a coordinated use of the network of ground-based telescopes in the southern hemisphere. We will soon finish implementing dedicated software subsystem consisted of automated observation scheduler and data pipeline for the sake of increased discovery rate, rapid follow-up, timely phase coverage, and efficient data analysis. We will give a brief introduction to test runs conducted at CTIO with the first KMTNet telescope in February and March 2015 and experimental data processing. Preliminary scientific results will also be presented.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.33 no.6
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• pp.2601-2610
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• 2013

The main limiting factors of Precise Point Positioning(PPP) accuracy are errors in broadcast satellite orbits, clock errors, and the others, which are receiver-dependent errors(ionospheric, tropospheric refraction, multipath, and tides, etc.). Therefore, to facilitate high precision PPP, precise orbits/clocks corrections, the receiver-dependent errors corrections have to apply to multi frequency GNSS measurements for an ionosphere free combination and integer ambiguity resolution in real-time. Currently, there are many Analysis Centers, which offer the precise corrections stream computed in real-time using the global or regional GNSS tracking network. The goles of this research considered performances of the real-time static PPP with using RTCM corrections from NTRIP casters. For this, the corrections streams of Analysis Centers received via NTRIP does apply to GNSS data of check points individually, as well as jointly, in accordance with various session lengths. After that, have compared the PPP results from the corrections streams with each other, and with Standard Point Positioning(SPP) results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.71-78
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• 2005

In this paper, we propose a transceiver for noncoherent OOK(On-Off Keying) Ultra Wide Band system based on magnitude detection. The proposed transceiver are designed using 0.18 micron CMOS technology and verified by simulation using SPICE and measurement. The proposed transceiver consist of parallelizer, Analog-to-Digital converter, clock generator, PLL and impulse generator. The time resolution of 1ns is obtained with 125MHz system clocks and 8x parallelization is carried out. The synchronized eight outputs with 2-bit resolution are delivered to the baseband. Impulse generator produces 1ns width pulse using digital CMOS gates. The simulation results and measurement show the feasibility of the proposed transceiver for UWB communication system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1069-1073
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• 2016

The Internet of Things (IoT) is the interconnection of uniquely identifiable embedded computing devices within the existing Internet infrastructure. IoT is expected to offer advanced connectivity of devices, systems, and services that goes beyond machine-to-machine communications and covers a variety of protocols, domains, and applications. Key system-level features that IoT needs to support can be summarized as device heterogeneity, scalability, ubiquitous data exchange through proximity wireless technologies, energy optimized solutions, localization and tracking capabilities, self-organization capabilities, semantic interoperability and data management, embedded security and privacy-preserving mechanisms. Time information is a critical piece of infrastructure for any distributed system. Time information and time synchronization are also fundamental building blocks in the IoT. The IoT requires new paradigms for combining time and data. This paper reviews conventional time keeping mechanisms in the Internet and presents issues to be considered for combining time and data in the IoT.