• Earthquakes and Structures
• /
• v.18 no.5
• /
• pp.637-648
• /
• 2020

In this study, a new steel cylindrical shell configuration of the dissipative energy device is proposed to improve lateral ductility and to reduce the damage of the structures against seismic forces. Four nested-eccentric- cylindrical shells are used to constructing this device; therefore, this proposed device is named nested-eccentric-cylindrical shells damper (NECSD). The particular configuration of the nested-eccentric-cylindrical shells is applied to promote the mechanical characteristics, stability, and overall performance of the damper in cyclic loads. Shell-type components are performed as a combination of series and parallel non-linear springs into the in-plan plastic deformation. Numerical analysis with respect to dimensional variables are used to calculate the mechanical characteristics of the NECSD, and full-scale testing is conducted for verifying the numerical results. The parametric study shows the NECSD with thin shells were more flexible, while devices with thick shells were more capacious. The results from numerical and experimental studies indicate that the NECSD has a stable behavior in hysteretic loops with highly ductile performance, and can provide appropriate dissipated energy under cyclic loads.

• Journal of the Korea Convergence Society
• /
• v.6 no.3
• /
• pp.51-57
• /
• 2015

This paper proposes an efficient method such as Extended Three Region Partitioning Method for nested loops with irregular dependences for maximizing parallelism. Our approach is based on the Convex Hull theory, and also based on minimum dependence distance tiling, the unique set oriented partitioning, and three region partitioning methods. In the proposed method, we eliminate anti dependences from the nested loop by variable renaming. After variable renaming, we present algorithm to select one or more appropriate lines among given four lines such as LMLH, RMLH, LMLT and RMLT. If only one line is selected, the method divides the iteration space into two parallel regions by the selected line. Otherwise, we present another algorithm to find a serial region. The selected lines divide the iteration space into two parallel regions as large as possible and one or less serial region as small as possible. Our proposed method gives much better speedup and extracts more parallelism than other existing three region partitioning methods.

• Journal of the Korea Computer Industry Society
• /
• v.3 no.8
• /
• pp.981-988
• /
• 2002

In this paper, a simple parallel compiler of a sequential loop is presented. This is a procedure for the automatic conversion of a sequential loop into a nested parallel DOALL loops at compile time. For this. the source program of Parafrase II parallel compiler is analyzed and a new general method the extracting parallelism in order to parallel processing effectively in nested loop is implemented.

• The Transactions of the Korea Information Processing Society
• /
• v.5 no.6
• /
• pp.1494-1506
• /
• 1998

본 논문에서는 루프구조의 효율적인 병렬수행을 위한 병렬성 추출에 대하여 불변과 가변 종속거리에 모두적용할 수 있는 통합된 새로운 기법을 제시한다. 이것은 컴파일시간에 순차 루프를 중첩된 DOALL 루프로의 자동 변환에 대한 절차로서, 중첩 루프의 전체적인 병렬화를 하기 위하여 문장들을 반복적으로 수행시키는 것에 의해서 자료 종속을 효과적으로 제거하는 알고리즘이다. 본 논문에 제시된 방법은 성능평가에서도 매우 뛰어난 방법임을 보였다.

• Proceedings of the Korea Contents Association Conference
• /
• 2014.11a
• /
• pp.289-290
• /
• 2014

본 논문에서는 중첩된 반복문에서 레이블을 사용하지 않고 프로그램의 흐름을 제어하는 개선된 문법구조를 제안한다. 또한 명시적으로 반복문의 종료 상태를 확인하는 방법을 제안한다. 제안된 방법을 사용하면 흐름 파악이 쉬운 프로그램을 작성할 수 있다.

• Journal of the Korean Society of Industry Convergence
• /
• v.5 no.2
• /
• pp.141-146
• /
• 2002

Stereolithography is the best known as rapid prototyping system. It uses the STL format data which is generated from CAD system. In this study, One of the main function of this developed CAM system deals with shape modification which divide a shape into two parts or more. The cross section of a STL part by a z-level is composed with nested or single polygonal closed loop. In order to make RP product, closed loops must fill with triangular facets from SSET and recover sliced triangular facets which is located normal direction to the cross sectional plane. The system is development by using Visuall C++ compiler in the environment of pentium PC. Operating system is Windows NT workstaion from Micro-Soft.

• Journal of the Korea Computer Industry Society
• /
• v.4 no.4
• /
• pp.501-508
• /
• 2003

In this paper A new theory of linear loop transformation called Elimination of Data Dependency(BDD) is presented. The current framework of linear loop transformation cannot identify a significant fraction of parallelism. For this reason, a method to extract the maximum loop parallelism in perfect nested loops is presented. This technique is applicable to general loop nests where the dependence include both distance and directions.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.30 no.8 s.251
• /
• pp.889-896
• /
• 2006

The concept of reliability has been applied to the topology optimization based on a reliability index approach or a performance measure approach. Since these approaches, called double-loop single vector approach, require the nested optimization problem to obtain the most probable point in the probabilistic design domain, the time for the entire process makes the practical use infeasible. In this work, new reliability-based topology optimization method is proposed by utilizing single-loop single-vector approach, which approximates searching the most probable point analytically, to reduce the time cost. The results of design examples show that the proposed method provides efficiency curtailing the time for the optimization process and accuracy satisfying the specified reliability.

• Journal of the Institute of Convergence Signal Processing
• /
• v.8 no.4
• /
• pp.285-292
• /
• 2007

SoC which deploys software modules as well as hardware IPs on a single chip is a major revolution taking place in the implementation of a system design, and high-level synthesis is an important process of SoC design methodology. Recently, SPARK parallelizing high-level synthesis software tool has been developed. It takes a behavioral ANSI-C code as an input, schedules it using code motion and various code transformations, and then finally generates synthesizable RTL VHDL code. Although SPARK employs various loop transformation algorithms, the synthesis results generated by SPARK are not acceptable for basic signal and image processing algorithms with nested loop. In this paper we propose a SoC platform with an application-specific PLD targeting local operations which are feature of many loop algorithms used in signal and image processing, and demonstrate design process which maps behavioral specification with nested loops written in a high-level language (ANSI-C) onto 2D systolic array. Finally the derived systolic array is implemented on the proposed application-specific PLD of SoC platform.

• The Transactions of the Korea Information Processing Society
• /
• v.5 no.8
• /
• pp.1997-2012
• /
• 1998

It is necessary to find out the parallelism in tlle sequential Java program to execute it on the parallel machine. The loop is a fundamental source to exploit parallelism as it process a large portion of total execution time in sequential Java program on the parallel machine. However, a complete parallel execution can hardly be achieved due to data dependence. This paper proposes the method of exploiting the implicit parallelism by structuring a dependence graph through the analysis of data dependence in the existing Java programming language having a nested loop structure. The parallel code generation method through the restructuring compiler and also the translation method of Java source program into multithread statement. which is supported by the Java programming language itself, are proposed here. The perforance evaluatlun of the program translaed into the thread statement is conducted using the trip cunt of loop and the trip Count of luop and the thread count as parameters The resttucturing compiler provides efficient way of exploiting parallelism by reducing manual overhead conveliing sequential Java program into parallel code. The execution time for the Java program as a result can be reduced un the parallel machine.