• Title/Summary/Keyword: Negative Loop

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Loop-mediated isothermal amplification assay for differentiation of Mycobacterium bovis and M. tuberculosis (Mycobacterium bovis와 M. tuberculosis 감별을 위한 등온증폭법)

  • Koh, Ba-Ra-Da;Kim, Jae-Myung;Sung, Chang-Min;Ji, Tae-Kyung;Na, Ho-Myung;Park, Seong-Do;Kim, Yong-Hwan;Kim, Eun-Sun
    • Korean Journal of Veterinary Service
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    • v.36 no.2
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    • pp.79-86
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    • 2013
  • Mycobacterium (M.) bovis, a member of the M. tuberculosis complex (MTC), is a re-emerging, zoonotic agent of bovine tuberculosis whose prevalence probably depends on variations in direct exposure to cattle and ingestion of raw milk. Accurate species differentiation of M. bovis and M. tuberculosis is needed to distinguish between human and zoonotic tuberculosis. This study successfully developed a loop-mediated isothermal amplification (LAMP) assay for rapid detection and differentiation of M. bovis and M. tuberculosis, however showed negative reactions in eight non-tuberculous mycobacteria (NTM) samples and ten other bacterial species. Sensitivity of this assay for detection of genomic M. bovis DNA was 10 $fg/{\mu}l$. And this assay successfully detected M. bovis in bovine clinical specimens. In conclusion, the LAMP assay is a simple and powerful tool for rapid detection of M. bovis in both pure bacterial culture and in clinical samples.

Design and Fabrication of a GaAs MESFET MMIC Transmitter for 2.4 GHz Wireless Local Loop Handset (2.4 GHz WLL 단말기용 GaAs MESFET MMIC 송신기 설계 및 제작)

  • 성진봉;홍성용;김민건;김해천;임종원;이재진
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.11 no.1
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    • pp.84-92
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    • 2000
  • A GaAs MESFET MMIC transmitter for 2.4 GHz wireless local loop handset is designed and fabricated. The transmitter consists of a double balanced active mixer and a two stage driver amplifier with voltage negative feedback. In particular, a pair of CS-CG(common source-common gate) structure compensates the reduction in dynamic range caused by unbalanced complementary IF input signals. And to suppress the leakage local power at RF port, the mixer is designed by using phase characteristic between the ports of MESFET. At the bias condition of 2.7 V and 55.2 mA, the fabricated MMIC transmitter with chip dimensions of $0.75\times1.75 mm^2$ obtains a measured conversion gain of 38.6 dB, output $P_{idB}$ of 11.6 dBm, and IMD3 at -5 dBm RF output power of -31.3 dBc. This transmitter is well suited for WLL handset.

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Analysis and Design of High Efficiency Feedforward Amplifier Using Distributed Element Negative Group Delay Circuit (분산 소자 형태의 마이너스 군지연 회로를 이용한 고효율 피드포워드 증폭기의 분석 및 설계)

  • Choi, Heung-Jae;Kim, Young-Gyu;Shim, Sung-Un;Jeong, Yong-Chae;Kim, Chul-Dong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.6
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    • pp.681-689
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    • 2010
  • We will demonstrate a novel topology for the feedforward amplifier. This amplifier does not use a delay element thus providing an efficiency enhancement and a size reduction by employing a distributed element negative group delay circuit. The insertion loss of the delay element in the conventional feedforward amplifier seriously degrades the efficiency. Usually, a high power co-axial cable or a delay line filter is utilized for a low loss, but the insertion loss, cost and size of the delay element still acts as a bottleneck. The proposed negative group delay circuit removes the necessity of the delay element required for a broadband signal suppression loop. With the fabricated 2-stage distributed element negative group delay circuit with -9 ns of total group delay, a 0.2 dB of insertion loss, and a 30 MHz of bandwidth for a wideband code division multiple access downlink band, the feedforward amplifier with the proposed topology experimentally achieved a 19.4 % power added efficiency and a -53.2 dBc adjacent channel leakage ratio with a 44 dBm average output power.

Characteristics of Open-Loop Current Sensor with Temperature Compensation Circuit (온도보상회로를 부착한 개방형 전류측정기의 특성)

  • Ku, Myung-Hwan;Park, Ju-Gyeong;Cha, Guee-Soo;Kim, Dong-Hui;Choi, Jong-Sik
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.12
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    • pp.8306-8313
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    • 2015
  • Open-type current sensors have been commonly used for DC motor controller, AC variable controller and Uninterruptible Power Supply. Recently they have begun to be used more widely, as the growth of renewable energy and smart-grid in power system. Considering most of the open-type current sensors are imported, developing the core technology needed to produce open-type current sensors is required. This paper describes the development and test results of open-type current sensors. Design of C type magnetic core, selection and test of a Hall sensor, design of current source circuit and signal conditioning circuit are described. 100A class DIP(Dual In-line Package) type and SMD(Surface Mount Devide) type open-type current sensors was made and tested. Test results show that the developed open-type current sensor satisfies the accuracy requirement of 2% and linearity requirement of 2% at 100 A of DC and AC current of 60Hz. Temperature compensation was carried out by using a temperature compensation circuit with NTC(Negative Temperature Coefficient) thermistor and the effect of the temperature compensation are described.

Application of HPV DNA Testing in Follow-up after Loop Electrosurgical Excision Procedures in Northern Thailand

  • Khunamornpong, Surapan;Settakorn, Jongkolnee;Sukpan, Kornkanok;Kietpeerakool, Chumnan;Tantipalakorn, Charuwan;Suprasert, Prapaporn;Siriaunkgul, Sumalee
    • Asian Pacific Journal of Cancer Prevention
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    • v.16 no.14
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    • pp.6093-6097
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    • 2015
  • Background: HPV DNA testing has been recently introduced as an adjunct test to cytology in the follow-up of patients after treatment for cervical lesions using the loop electrosurgical excision procedure (LEEP). The aim of this study was to evaluate the role of HPV testing in the detection of persistent or recurrent disease after LEEP in patients with cervical epithelial lesions in northern Thailand. Materials and Methods: Patients who underwent LEEP as a treatment for histological low-grade (LSIL) or high-grade squamous intraepithelial lesion (HSIL) or worse at Chiang Mai University Hospital between June 2010 and May 2012 were included. Follow-ups were scheduled at 6-month intervals and continued for 2 years using co-testing (liquid-based cytology and Hybrid Capture 2 [HC2]) at 6 months and 24 months and liquid-based cytology alone at 12 and 18 months. Results: Of 98 patients included, the histological diagnoses for LEEP included LSIL in 16 patients, and HSIL or worse in 82 patients. The LEEP margin status was negative in 84 patients (85.7%). At follow-up, 10 patients (10.2%) had persistent/recurrent lesions; 4 among LSIL patients (25.0%) and 6 in the group with HSIL or worse (7.3%). Only 2 of 82 patients (2.4%) with HSIL or worse diagnoses had histological HSIL in the persistent/recurrent lesions. Using histologically confirmed LSIL as the threshold for the detection of persistent/recurrent disease, cytology had a higher sensitivity than HC2 (90.0% versus 70.0%). At the 6-month follow-up appointment, combined cytology and HC2 (co-testing) had a higher sensitivity in predicting persistent/recurrent disease (80.0%) compared with that of cytology alone (70.0%) and HC2 (50.0%). Conclusions: After LEEP with a negative surgical margin, the rate of persistent/recurrent lesions is low. The addition of HPV testing at the 6-month visit to the usual cytology schedule may be an effective approach in the follow-up after LEEP.

Regulation of Arabidopsis Circadian Clock by De-Etiolated 1 (DET1) Possibly via Histone 3 Acetylation (H3Ac) (히스톤 3 아세틸화(H3Ac)를 통한 De-Etiolated 1 (DET1)의 애기장대 생체시계 조절)

  • Song, Hae-Ryong
    • Journal of Life Science
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    • v.22 no.8
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    • pp.999-1008
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    • 2012
  • The circadian clock is a self-sustaining 24-hour timekeeper that allows organisms to anticipate daily-changing environmental time cues. Circadian clock genes are regulated by a transcriptional-translational feedback loop. In Arabidopsis, LATE ELONGATED HYPOCOTYL (LHY) and CIRCADIAN CLOCK-ASSOCIATED 1 (CCA1) transcripts are highly expressed in the morning. Translated LHY and CCA1 proteins repress the expression of the TIMING OF CAB EXPRESSION 1 (TOC1) transcripts, which peaks in the evening. The TOC1 protein elevates the expression of the LHY and CCA1 transcripts, forming a negative feedback loop that is believed to constitute the oscillatory mechanism of the clock. In mammals, the transcription factor protein CLOCK, which is a central component of the circadian clock, was reported to have an intrinsic histone acetyltransferase (HAT) activity, suggesting that histone acetylation is important for core clock mechanisms. However, little is known about the components necessary for the histone acetylation of the Arabidopsis clock-related genes. Here, I report that DET1 (De-Etiolated1) functions as a negative regulator of a key component of the Arabidopsis circadian clock gene LHY in constant dark phases (DD) and is required for the down-regulation of LHY expression through the acetylation of histone 3 (H3Ac). However, the HATs directly responsible for the acetylation of H3 within LHY chromatin need to be identified, and a link connecting the HATs and DET1 protein is still absent.

Analysis of Elements for Efficiencies in Magnetically-Coupled Wireless Power Transfer System Using Metamaterial Slab (메타물질 Slab이 포함된 자계 결합 무선 전력 전송 시스템 효율 요소 분석)

  • Kim, Gunyoung;Oh, TaekKyu;Lee, Bomson
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.25 no.11
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    • pp.1128-1134
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    • 2014
  • In this paper, the effects of a metamaterial slab with negative permeability in a magnetically coupled wireless power transfer system (WPT) in the overall performance are analyzed quantitatively in terms of the effective quality factors of the loop resonators and coupling coefficient considering the slab losses, based on an equivalent circuit. Using the ideal metamaterial slab(lossless slab), the WPT efficiency is improved considerably by the magnetic flux focusing. However, the practical lossy slab made of RRs or SRRs limits the significant enhancement of WPT efficiency due to the relatively high losses in the slab consisting of RRs or SRRs near the resonant frequency. For the practical loop resonator, other than a point magnetic charge, using the practical lossy metamaterial slab in order to improve the transfer efficiency, the width of the slab needs to be optimized somewhat less than the half of the distance between two loop resonators. For the low-loss slab with its loss tangent of 0.001, the WPT efficiency is maximized at 93 % when the ratio of the slab width and the distance between the two resonators is approximately 0.35, compared with 53 % for the case without the slab. The efficiency in case of employing the high-low slab(loss tangent: 0.2) is maximized at 61 % when the slab ratio is 0.25.

Degradation from Polishing Damage in Ferroelectric Characteristics of BLT Capacitor Fabricated by Chemical Mechanical Polishing Process (화학적기계적연마 공정으로 제조한 BLT Capacitor의 Polishing Damage에 의한 강유전 특성 열화)

  • Na, Han-Yong;Park, Ju-Sun;Jung, Pan-Gum;Ko, Pil-Ju;Kim, Nam-Hoon;Lee, Woo-Sun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.236-236
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    • 2008
  • (Bi,La)$Ti_3O_{12}$(BLT) thin film is one of the most attractive materials for ferroelectric random access memory (FRAM) applications due to its some excellent properties such as high fatigue endurance, low processing temperature, and large remanent polarization [1-2]. The authors firstly investigated and reported the damascene process of chemical mechanical polishing (CMP) for BLT thin film capacitor on behalf of plasma etching process for fabrication of FRAM [3]. CMP process could prepare the BLT capacitors with the superior process efficiency to the plasma etching process without the well-known problems such as plasma damages and sloped sidewall, which was enough to apply to the fabrication of FRAM [2]. BLT-CMP characteristics showed the typical oxide-CMP characteristics which were related in both pressure and velocity according to Preston's equation and Hernandez's power law [2-4]. Good surface roughness was also obtained for the densification of multilevel memory structure by CMP process [3]. The well prepared BLT capacitors fabricated by CMP process should have the sufficient ferroelectric properties for FRAM; therefore, in this study the electrical properties of the BLT capacitor fabricated by CMP process were analyzed with the process parameters. Especially, the effects of CMP pressure, which had mainly affected the removal rate of BLT thin films [2], on the electrical properties were investigated. In order to check the influences of the pressure in eMP process on the ferroelectric properties of BLT thin films, the electrical test of the BLT capacitors was performed. The polarization-voltage (P-V) characteristics show a decreased the remanent polarization (Pr) value when CMP process was performed with the high pressure. The shape of the hysteresis loop is close to typical loop of BLT thin films in case of the specimen after CMP process with the pressures of 4.9 kPa; however, the shape of the hysteresis loop is not saturated due to high leakage current caused by structural and/or chemical damages in case of the specimen after CMP process with the pressures of 29.4 kPa. The leakage current density obtained with positive bias is one order lower than that with negative bias in case of 29.4 kPa, which was one or two order higher than in case of 4.9 kPa. The high pressure condition was not suitable for the damascene process of BLT thin films due to the defects in electrical properties although the better efficiency of process. by higher removal rate of BLT thin films was obtained with the high pressure of 29.4 kPa in the previous study [2].

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Feasibility Model Development by Applying System Dynamics Method in Residential Officetel (시스템다이내믹스를 활용한 오피스텔 사업타당성 분석 모델 개발)

  • Jang, Jun-Ho;Ha, Sun-Geun;Kim, Kyeong-Ryoung;Son, Ki-Young;Son, Seung-Hyun;Lee, Taick-Oun
    • Journal of the Korea Institute of Building Construction
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    • v.18 no.3
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    • pp.285-294
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    • 2018
  • Due to the low interest rates of banks according to the breakdown economy after the global financial crisis in 2008 As a substitute for financial products, the investment demand has been increased for rentable investment funds such as commercial building and officetel. However, the problems such as oversupply, decrease of a rental profit and negative perception of development projects have been occurred. One of the primary problems is the existing deterministic method of project feasibility analysis. Therefore, the objective of this study is to develop feasibility model by applying system dynamics method in residential officetel. To achieve the objective, first, the previous studies are investigated. Second, the causal loop diagram is structured based on the collected data. Third, the feasibility model is developed through the causal loop diagram. Fourth, the effectiveness is validated and compared to collected actual data. The proposed model can be helpful whether or not conduct execution of an officetel development project to the decision makers.

Advanced Synchronous Reference Frame Controller for three-Phase UPS Powering Unbalanced and Nonlinear Loads (3상 무정전 전원장치에 적합한 새로운 구조의 동기좌표계 전압제어기)

  • Hyun Dong-Seok;Kim Kyung-Hwan
    • The Transactions of the Korean Institute of Power Electronics
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    • v.10 no.5
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    • pp.508-517
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    • 2005
  • This paper describes a high performance voltage controller for 3-phase 4-wire UPS (Uninterruptible Power Supply) system, and proposes a new scheme of synchronous reference frame controller in order to compensate for the voltage distortions due to unbalanced and nonlinear loads. Proposed scheme can eliminate the negative sequence voltage component due to unbalanced loads and also reduce the harmonic voltage component due to non-linear loads, even when the bandwidth of voltage control loop is a very low. In order to compensate for the effects of unbalanced loads, the synchronous reference frame controller with the positive and negative sequence computation block is proposed, and the synchronous frame controller with a bandpass filter is proposed to compensate for the selected harmonic frequency of output voltage. The effectiveness of the proposed scheme has been investigated and verified through computer simulations and experiments by a 30kVA UPS.