• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.560-561
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• 2022

In this paper, current-voltage characteristics of various types of Nanosheet FET (NSFET) and FinFET are simulated with 3D device simulator. The threshold voltage and subthreshold swing extracted from the simulated current-voltage characteristics of NSFET and FinFET were compared. Both of threshold voltage and drain current of NSFET are higher than those of FinFET. The subthreshold voltage swing (SS) of NSFET is steeper than that of FinFET.

• Nuclear Engineering and Technology
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• v.56 no.11
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• pp.4679-4687
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• 2024

This study analyzes the single-event transient (SET) characteristics of alpha particles on multi-channel Forksheet-FET and Nanosheet-FET at the device and circuit levels through 3D TCAD simulations. The study investigates the differences in SET responses based on the energy and incident position of incoming alpha particles, considering the structural variances between Forksheet-FET and Nanosheet-FET, as well as the presence or absence of bottom dielectric isolation (BDI) in the fabrication process. Specifically, the introduction of BDI is observed to significantly suppress the voltage drop caused by 'unintended' current, as it can block the substantial electron-hole pairs (EHP) generated by injected alpha particles in the bulk substrate from reaching the FET terminals. Furthermore, it was confirmed that the size of abnormal current decreases as the energy of the injected alpha particle increases. Additionally, evaluating the response to SET based on the fundamental logic circuit, the CMOS inverter, revealed relatively small abnormal voltage drops for both Forksheet and Nanosheet when BDI was applied, confirming high immunity to radiation effects. Moreover, it can be observed that the application of BDI enhances reliability from a memory perspective by effectively suppressing voltage flips in the SRAM's cross-coupled latch circuit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.121-122
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• 2022

In this paper, the device performance with the structure of Nanosheet FET (NSFET) and FinFET is simulated through a three-dimensional device simulator. Current-voltage characteristics of NSFET and FinFET were simulated with respect to channel doping concentrations, and the performance such as threshold voltage and subthreshold swing extracted from the current-voltage characteristics was compared. NSFET flows more drain current and has a higher threshold voltage in current-voltage characteristics depending on channel doping concentration than that of FinFET. The subthreshold voltage swing (SS) of NSFET is steeper than that of FinFET

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.1
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• pp.50-57
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• 2022

Reliability of CMOS has been severed under aggressive device scaling. Conventional technologies such as lightly doped drain (LDD) and forming gas annealing (FGA) have been applied for better device reliability, but further advances are modest. Alternatively, electro-thermal annealing (ETA) which utilizes Joule heat produced by electrodes in a MOSFET, has been newly introduced for gate dielectric curing. However, concerns about mechanical stability during the electro-thermal annealing, have not been discussed, yet. In this context, this paper demonstrates the mechanical stability of nanosheet FET during the electro-thermal annealing. The effect of mechanical stresses during the electro-thermal annealing was investigated with respect to device design parameters.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.136-141
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• 2023

The continuous shrinking of transistors in integrated circuits leads to difficulties in improving performance, resulting in the emerging transistors such as nanosheet field-effect transistors. In this paper, we propose a TCAD-machine learning framework of nanosheet FETs to model the current-voltage characteristics. Sentaurus TCAD simulations of nanosheet FETs are performed to obtain a large amount of device data. A machine learning model of I-V characteristics is trained using the multi-layer perceptron from these TCAD data. The weights and biases obtained from multi-layer perceptron are implemented in a PSPICE netlist to verify the accuracy of I-V and the DC transfer characteristics of a CMOS inverter. It is found that the proposed machine learning model is applicable to the prediction of nanosheet field-effect transistors device and circuit performance.

• Nanomaterials
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• v.12 no.22
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• pp.4096-4107
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• 2022

In this work, a hybrid-phase transition field-effects-transistor (hyper-FET) integrated with phase-transition materials (PTM) and a multi-nanosheet FET (mNS-FET) at the 3 nm technology node were analyzed at the device and circuit level. Through this, a benchmark was performed for presenting device design guidelines and for using ultra-low-power applications. We present an optimization flow considering hyper-FET characteristics at the device and circuit level, and analyze hyper-FET performance according to the phase transition time (TT) and baseline-FET off-leakage current (I_OFF) variations of the PTM. As a result of inverter ring oscillator (INV RO) circuit analysis, the optimized hyper-FET increases speed by +8.74% and reduces power consumption by -16.55%, with IOFF = 5 nA of baseline-FET and PTM TT = 50 ps compared to the conventional mNS-FET in the ultra-low-power region. As a result of SRAM circuit analysis, the read static noise margin is improved by 43.9%, and static power is reduced by 58.6% in the near-threshold voltage region when the PTM is connected to the pull-down transistor source terminal of 6T SRAM for high density. This is achieved at 41% read current penalty.