• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.7-8
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• 2007

We investigated the characteristics of UTB-SOI pMOSFETs with SOI thickness ($T_{SOI}$) ranging from 10 nm to 1 nm and evaluated the dependence of electrical characteristics on the silicon surface orientation. As a result, it is found that the subthreshold characteristics of (100)-surface UTB-SOI pMOSFETs were superior to (110)-surface. However, the hole mobility of (110)-surface were larger than that of (100)-surface. The enhancement of effective hole mobility at the effective field of 0.1 MV/ccm was observed from 3-nm to 5-nm SOI thickness range.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.175-177
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• 2002

Electrical characteristics of the Si-O superlattice diode as a function of annealing conditions have been studied. The nanocrystalline silicon/adsorbed oxygen superlattice formed by molecular beam epitaxy (MBE) system. Consequently, the experimental results of superlattice diode with multilayer Si-O structure showed the stable and good insulating behavior with high breakdown voltage. This is very useful promise for Si-based optoelectronic and quantum device as well as for the replacement of silicon-on-insulator (SOI) in ultra high speed and lower power CMOS devices in the future, and it can be readily integrated with silicon ULSI processing.

• Proceedings of the Korean Magnestics Society Conference
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• 2004.12a
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• pp.31-32
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• 2004

• Proceedings of the Korean Vacuum Society Conference
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• 2008.02a
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• pp.132-132
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• 2008

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.99-100
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• 2006

Silicon-on-insulator(SOI) MOSFET with SiGe/Si heterostructure channel is an attractive device due to its potent use for relaxing several limits of CMOS scaling, as well as because of high electron and hole mobility and low power dissipation operation and compatibility with Si CMOS standard processing. SOI technology is known as a possible solution for the problems of premature drain breakdown, hot carrier effects, and threshold voltage roll-off issues in sub-deca nano-scale devices. For the forthcoming generations, the combination of SiGe heterostructures and SOI can be the optimum structure, so that we have developed SOI n-MOSFETs with SiGe/Si heterostructure channel grown by reduced pressure chemical vapor deposition. The SOI n-MOSFETs with a SiGe/Si heterostructure are presented and their DC characteristics are discussed in terms of device structure and fabrication technology.

• Proceedings of the Korean Vacuum Society Conference
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• 2004.08a
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• pp.66-67
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• 2004

• Transactions of the Korean Society of Mechanical Engineers B
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• v.41 no.6
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• pp.409-414
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• 2017

The aim of this study is to understand the phonon transfer characteristics of a silicon thin film transistor. For this purpose, the Joule heating mechanism was considered through the electron-phonon interaction model whose validation has been done. The phonon transport characteristics were investigated in terms of phonon mean free path for the variations in the device power and silicon layer thickness from 41 nm to 177 nm. The results may be used for developing the thermal design strategy for achieving reliability and efficiency of the silicon-on-insulator (SOI) transistor, further, they will increase the understanding of heat conduction in SOI systems, which are very important in the semiconductor industry and the nano-fabrication technology.

• Journal of the Korean Vacuum Society
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• v.17 no.2
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• pp.156-159
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• 2008

The electrical characteristic of SiGe-on-SOI (SGOI) wafer with different Ge concentration were evaluated by pseudo-MOSFET. Epitaxial SiGe layers was grown directly on top of SOI with Ge concentrations of 16.2, 29.7, 34.3 and 56.5 at.%. As Ge concentration increased, leakage current increased and threshold voltage shifted from 3 V to 7 V in nMOSFET, from -7 V to -6 V in pMOSFET. The interface states between buried oxide and top of Si was significantly increased by the rapid thermal annealing (RTA) process, and so the electrical characteristic of SGOI wafer degraded. On the other hand, additional post RTA　annealing (PRA) showed that it was effective in decreasing the interface states generated by RTA processes and the electrical characteristic of SGOI wafer enhanced higher than initial state.

• Biotechnology and Bioprocess Engineering:BBE
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• v.11 no.6
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• pp.530-537
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• 2006

Recently isolated, Pseudomonas putida SN1 grows on styrene as its sole carbon and energy source through successive oxidation of styrene by styrene monooxygenase (SMO), styrene oxide isomerase (SOI), and phenylacetaldehyde dehydrogenase. For the production of (S)-styrene oxide, two knockout mutants of SN1 were constructed, one lacking SOI and another lacking both SMO and SOI. These mutants were developed into whole-cell biocatalysts by transformation with a multicopy plasmid vector containing SMO genes (styAB) of the SN1. Neither of these self-cloned recombinants could grow on styrene, but both converted styrene into an enantiopure (S)-styrene oxide (e.e. > 99%). Whole-cell SMO activity was higher in the recombinant constructed from the SOI-deleted mutant (130 U/g cdw) than in the other one (35 U/g cdw). However, the SMO activity of the former was about the same as that of the SOI-deleted SN1 possessing a single copy of the styAB gene that was used as host. This indicates that the copy number of styAB genes is not rate-limiting on SMO catalysis by whole-cell SN1.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.208-211
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• 1997

We have fabricated a single-electron-tunneling(SET) transistor with a dual gate geometry based on the SOI structure prepared by SIMOX wafers. The split-gate is the lower-gate is the lower-level gate and located ∼ 100${\AA}$ right above the inversion layer 2DEG active channel, which yields strong carrier confinement with fully controllable tunneling potential barrier. The transistor is operating at low temperatures and exhibits the single electron tunneling behavior through nano-size quantum dot. The Coulomb-Blockade oscillation is demonstrated at 15mK and its periodicity of 16.4mV in the upper-gate voltage corresponds to the formation of quantum dots with a capacity of 9.7aF. For non-linear transport regime, Coulomb-staircases are clearly observed up to four current steps in the range of 100mV drain-source bias. The I-V characteristics near the zero-bias displays typical Coulomb-gap due to one-electron charging effect.