• Proceedings of the Materials Research Society of Korea Conference
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• 2006.05a
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• pp.17.2-17.2
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• 2006

• Korean Journal of Materials Research
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• v.14 no.6
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• pp.413-419
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• 2004

Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.711-714
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• 2003

In this presentation, we investigated the abnormal subthreshold slope of the FD SOI MOSFETs upon the rapid thermal annealing. Based on subthreshold technique and C-V measurement, we deduced that the hump of the subthreshold slope comes from the abnormal D$_{it}$ distribution after RTA. The local kink in the interface trap density distribution by RTA drastically degrades the subthreshold characteristics and mini hump can be eliminated by S-PGA.A.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.7-8
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• 2005

The pseudo MOSFET measurement technique has been a simple and rapid method for characterization of SOI wafers without any device fabrication process. We adopted the pseudo MOSFET technique to examine the surface silicon film thickness dependence of electrical properties of SOI wafer. The measurements showed that turn-on voltage increased and electron mobility decreased as the SOI film thickness was reduced in the SOI film thickness of less than 20 nm region.

• Journal of Sensor Science and Technology
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• v.14 no.6
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• pp.387-394
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• 2005

In order to design SOI CMOS image sensors, SOI MOSFET model parameters were extracted using the equation of bulk MOSFET model parameters and were optimized using SPICE level 2. Simulated I-V characteristics of the SOI NMOSFET using the extracted model parameters were compared to the experimental I-V characteristics of the fabricated SOI NMOSFET. The simulation results agreed well with experimental results. A unit pixel for SOI CMOS image sensors was designed and was simulated for the PPS, APS, and logarithmic circuit using the extracted model parameters. In these CMOS image sensors, a nano-wire MOSFET photodetector was used. The output voltage levels of the PPS and APS are well-defined as the photocurrent varied. It is confirmed that SOI CMOS image sensors are faster than bulk CMOS image sensors.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.239-242
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• 2004

We investigated the nanotopography impact on the post-chemical mechanical polishing (post-CMP) oxide thickness deviation(OTD) of ceria slurry with a surfactant. Not only the surfactant but also the slurry abrasive size influenced the nanotopography impact. The magnitude of the post-CMP OTD increased with adding the surfactant in the case of smaller abrasives, but it did not increase in the case of larger abrasives, while the magnitudes of the nanotopography heights are all similar. We created a one-dimensional numercal simulation of the nanotopography impact by taking account of the non-Prestonian behavior of the slurry, and good agreement with experiment results was obtained.

• Journal of Sensor Science and Technology
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• v.11 no.5
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• pp.294-300
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• 2002

In this study, we fabricated thermopile infrared sensor with floating membrane structure. Floating membrane was formed by SOI(Silicon On Insulator) structure. In SOI structure, silicon dioxide layer between top silicon layer and bottom silicon substrate was etched by HF solution, then membrane was floated over substrate. After membrane was floated, thermopile pattern was formed on membrane. By insertion of SOI technology, we could obtain thermal isolation structure easily and passivation process for sensor pattern protection was not required during fabrication process. Then, the amplifier circuit for thermopile sensor was fabricated by using $1.5{\mu}m$ CMOS process. The voltage gain of fabricated amplifier was about two hundred.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.6
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• pp.487-490
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• 2007

In this paper, the formation and thermal stability characteristics of Ni silicide using Ni-V alloy on Boron cluster ($B_{18}H_{22}$) implanted bulk and SOI substrate were examined in comparison with pure Ni for nano-scale CMOSFET. The Ni silicide using Ni-V alloy on $B_{18}H_{22}$ implanted SOI substrate after high temperature post-silicidation annealing showed the lower sheet resistance, no agglomeration interface image and lower surface roughness than that using pure Ni. The thermal stability of Ni silicide was improved by using Ni-V alloy on $B_{18}H_{22}$ implanted SOI substrate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.1-6
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• 2002

For an optimum device design of nano-scale SOI devices, this paper describes the short channel effects of multi-gate structures SOI MOSFETs such as double gate, triple gate and quadruple gate, as well as a new proposed Pi gate using computer simulation. The simulation has been performed with different channel doping concentrations, channel widths, silicon film thickness, and vertical gate extension depths of Pi gate. From the simulation results, it is found that Pi gate devices have a large margin in determination of doping concentrations, channel widths and film thickness comparing to double and triple gate devices because Pi gate devices offer a better short channel effects.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.11
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• pp.1000-1004
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• 2006

In this paper, thermal stability of Ni-silicide formed on the SOI substrate with $B_{11}$ has been characterized. The sheet resistance of Ni-silicide on un-doped SOI and $B_{11}$ implanted bulk substrate was increased after the post-silicidation annealing at $700^{\circ}C$ for 30 min. However, in case of $B_{11}$ implanted SOI substrate, the sheet resistance showed stable characteristics after the post-silicidation annealing up to $700^{\circ}C$ for 30 min. The main reason of the excellent property of $B_{11}$ sample is believed to be the retardation of Ni diffusion by the boron and bottom oxide layer of SOI. Therefore, retardation of Ni diffusion is highly desirable lot high performance Ni silicide technology.