• Journal of the Microelectronics and Packaging Society
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• v.24 no.3
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• pp.7-11
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• 2017

In this paper, we have studied the characteristics of NAND Flash memory in SONOS Poly-Si Thin Film Transistor (Poly-Si TFT) device. Source/drain junctions(S/D) of cells were not implanted and selective transistors were located in the end of cells. We found the optimum conditions of process by means of the estimation for the doping concentration of channel and source/drain of selective transistor. As the doping concentration was increased, the channel current was increased and the characteristic of erase was improved. It was believed that the improvement of erase characteristic was probably due to the higher channel potential induced by GIDL current at the abrupt junction. In the condition of process optimum, program windows of threshold voltages were about 2.5V after writing and erasing. In addition, it was obtained that the swing value of poly Si TFT and the reliability by bake were enhanced by increasing process temperature of tunnel oxide.

• KIISE Transactions on Computing Practices
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• v.22 no.2
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• pp.95-100
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• 2016

In the current era of big data and cloud computing, the amount of data utilized is increasing, and various systems to process this big data rapidly are being developed. A distributed file system is often used to store the data, and glusterFS is one of popular distributed file systems. As computer technology has advanced, NAND flash SSDs (Solid State Drives), which are high performance storage devices, have become cheaper. For this reason, datacenter operators attempt to use SSDs in their systems. They also try to install glusterFS on SSDs. However, since the glusterFS is designed to use HDDs (Hard Disk Drives), when SSDs are used instead of HDDs, the performance is degraded due to structural problems. The problems include the use of I/O-cache, Read-ahead, and Write-behind Translators. By removing these features that do not fit SSDs which are advantageous for random I/O, we have achieved performance improvements, by up to 255% in the case of 4KB random reads, and by up to 50% in the case of 64KB random reads.

• Journal of KIISE
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• v.43 no.4
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• pp.411-418
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• 2016

In recent times, NAND flash memory has become widely used as secondary storage for computing devices. Accordingly, to take advantage of NAND flash memory, new file systems have been actively studied and proposed. The performance of these file systems is generally measured with benchmark tools. However, since benchmark tools are executed by software simulation methods, many researchers get non-uniform benchmark results depending on the system environments. In this paper, we use Filebench, one of the most popular and representative benchmark tools, to analyze benchmark results and study the reasons why the benchmark result variations occur. Our experimental results show the differences in benchmark results depending on the system environments. In addition, this study substantiates the fact that system performance is affected mainly by background I/O requests and fsync operations.

• Journal of the Korea Society of Computer and Information
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• v.13 no.3
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• pp.57-63
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• 2008

As diverse memory cards based on NAND flash memory are getting popularity with consumer electronics such as digital camera, camcorder and MP3 player the compatibility problems between a newly developed memory card and existent host systems have become a main obstacle to time-to-market delivery of product. The common practice for memory card compatibility test is to use a real host system as a test bed. As an improved solution, an FPGA-based prototyping board can be used for emulating host systems. However, the above approaches require a long set-up time and have limitations in representing various host and device systems. In this paper, we propose a co-validation environment for compatibility test between memory card and host system using formal modeling based on Esterel language and co-simulation methodology. Finally, we demonstrate the usefulness of the proposed environment with a case study of real memory card development.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.545-545
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• 2008

Poly-Si is an essential material for floating gate in NAND Flash memory. To fabricate this material within region of floating gate, chemical mechanical polishing (CMP) is commonly used process for manufacturing NAND flash memory. We use colloidal silica abrasive with alkaline agent, polymeric additive and organic surfactant to obtain high Poly-Si to SiO2 film selectivity and reduce surface defect in Poly-Si CMP. We already studied about the effects of alkaline agent and polymeric additive. But the effect of organic surfactant in Poly-Si CMP is not clearly defined. So we will examine the function of organic surfactant in Poly-Si CMP with concentration separation test. We expect that surface roughness will be improved with the addition of organic surfactant as the case of wafering CMP. Poly-Si wafer are deposited by low pressure chemical vapor deposition (LPCVD) and oxide film are prepared by the method of plasma-enhanced tetra ethyl ortho silicate (PETEOS). The polishing test will be performed by a Strasbaugh 6EC polisher with an IC1000/Suba IV stacked pad and the pad will be conditioned by ex situ diamond disk. And the thickness difference of wafer between before and after polishing test will be measured by Ellipsometer and Nanospec. The roughness of Poly-Si film will be analyzed by atomic force microscope.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.4
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• pp.35-39
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• 2019

The shielding effectiveness (SE) of the EMI spray coating film was measured in a three-dimensional structure. The shielding effectiveness was measured by AST D4935 using coaxial type TEM cell. A standard sample of the cylindrical slab is fabricated to measure the shielding effectiveness using the ASTM D4935. At this time, spray coating was performed by bonding a three-dimensional structure with NAND flash memory to a standard sample. In the case of spray coating, it was uniformly coated not only on the horizontal plane but also on the vertical plane of the three-dimensional structure. As a result of measurement, shielding effectiveness of maximum 59 dB was measured in a three-dimensional structure similar to the case without three-dimensional structure. As a result, it was confirmed that the spray coating can be uniformed even in the three-dimensional structure.

• Journal of Digital Convergence
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• v.20 no.5
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• pp.593-598
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• 2022

Recently, data production has seen explosive growth, and the storage systems to store these big data safely and quickly is evolving in various ways. A typical configuration of storage systems is the use of SSDs with fast data processing speed as a RAID group that can maintain reliable data. However, since NAND flash memory, which composes SSD, has the feature that deterioration if writes more than a certain number of times are repeated, can increase the likelihood of simultaneous failure on multiple SSDs in a RAID group. And this can result in serious reliability problems that data cannot be recovered. Thus, in order to solve this problem, we propose a method of throttling IOs so that each SSD within a RAID group leads to a different life-end. The technique proposed in this paper utilizes SMART to control the state of each SSD and the number of IOs allocated according to the data pattern used step by step. In addition, this method has the advantage of preventing large amounts of concurrency defects in RAID because it induces differential lifetime finishes of SSDs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.360-369
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• 2012

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

• The KIPS Transactions:PartA
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• v.13A no.5 s.102
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• pp.387-398
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• 2006

In this paper, we propose a new page allocation scheme for flash memory file system. The proposed scheme allocates pages by exploiting the concept of Purity, which is defined as the fraction of blocks where valid Pages and invalid Pages are coexisted. The Pity determines the cost of block cleaning, that is, the portion of pages to be copied and blocks to be erased for block cleaning. To enhance the purity, the scheme classifies hot-modified data and cold-modified data and allocates them into different blocks. The hot/cold classification is based on both static properties such as attribute of data and dynamic properties such as the frequency of modifications. We have implemented the proposed scheme in YAFFS and evaluated its performance on the embedded board equipped with 400MHz XScale CPU, 64MB SDRAM, and 64MB NAND flash memory. Performance measurements have shown that the proposed scheme can reduce block cleaning time by up to 15.4 seconds with an average of 7.8 seconds compared to the typical YAFFS. Also, the enhancement becomes bigger as the utilization of flash memory increases.

• Journal of Convergence for Information Technology
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• v.11 no.11
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• pp.44-50
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• 2021

Recently, enterprise storage systems that require large-capacity storage devices to accommodate big data have used large-capacity flash memory-based storage devices with high density compared to cost and size. This paper proposes a high-efficiency life prediction method with slope descent to maximize the life of flash memory media that directly affects the reliability and usability of large enterprise storage devices. To this end, this paper proposes the structure of a matrix for storing metadata for learning the frequency of defects and proposes a cost model using metadata. It also proposes a life expectancy prediction policy in exceptional situations when defects outside the learned range occur. Lastly, it was verified through simulation that a method proposed by this paper can maximize its life compared to a life prediction method based on the fixed number of times and the life prediction method based on the remaining ratio of spare blocks, which has been used to predict the life of flash memory.